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W90220F
W90220F
PA-RISC Embedded Controller
Version 0.84 March 1999
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W90220F
Table of Contents
TABLE OF CONTENTS 1. OVERVIEW 2. FEATURES 3. PIN CONFIGURATION 3.1 Pin Diagram 3.2 Detailed Pin Descriptions 4. CPU CORE 4.1 Overview 4.2 Block diagram 4.3 Features 4.4 PA-RISC Architecture 4.4.1 CPU Resources 4.4.2 Addressing Mode & Memory Map 4.4.3 Branch Control 4.4.4 Interrupt Control 4.5 Pipeline Operation 4.6 Implementation Dependent features 4.6.1 MultiMedia Extension Instruction Set 4.6.2 MAC unit and Releated Instruction Set 4.6.3 Diagnostic Instruction Set 4.6.4 Flush Instruction/Data Cache & Branch-Target-Buffer (BTB) 4.6.5 Level-0 Debug SFU 4.7 Power Management Unit 4.8 Serial ICE interface
5. MEGACELLS 5.1 Functional Descriptions 5.1.1 Memory Controller 5.1.2 DMA Controller 5.1.3 PCI Bridge 5.1.4 Parallel Port Interface (PPI) 5.1.5 UART
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5.1.6 Synchronous Serial Port Interface (SSI) 5.1.7 Timer Channels 5.2 Register Definitions 5.2.1 Memory Controller 5.2.2 DMA Controller 5.2.3 PCI Bridge 5.2.4 Parallel Port Interface (PPI) 5.2.5 UART 5.2.6 Synchronous Serial Port Interface (SSI) 5.2.7 Timer Channels 6. ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings 6.2 DC Specifications 6.3 AC Specifications 6.3.1 Memory Controller 6.3.2 DMA Controller 6.3.3 PCI Bridge 6.3.4 Parallel Port Interface (PPI) 6.3.5 UART 6.3.6 Synchronous Serial Port Interface (SSI) 6.3.7 Timer Channels 7. PACKAGE DIMENSIONS
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1. OVERVIEW
The W90220 is a high performance, highly integrated 32-bit processor intended for a wide range of embedded applications, such as videophone, internet devices, internetworking platform. Fig 1-1 shows a block diagram of the overall system. The W90220 consists of a 32-bit PA-RISC core, memory controller and integrated logics for I/O modules The PA-RISC core is equipped with 4 KBytes of instruction cache memory and 4 KBytes of data cache memory augmented with a dual-cycle multiply/accumulate module running up to 150 MHz. It allows to implement integrated DSP functions like software modem for high-performance standard data and fax protocols. A flexible power management scheme (under software control) and lots of low power circuits have been used to eliminate the chip's power consumption. The W90220 consume only 375 mA at its maximum speed (150 MHz) on a full-load system. The chip provides two 8-bit DMA channels, four 16-bit IDE I/O channels, a PCI bridge supporting up to four external PCI masters, a IEEE-1284 compliant parallel port interface (PPI), two RS232 type universal asynchronous serial port (UART), two timer channels, a flexible synchronous interface (SSI) connecting to an external audio or telephony codec devices, a proprietary serial ICE interface (SP-ICE) for software development and debugging. The chip has a high performance memory controller. The types of external memory devices supported include dynamic random access memory (DRAM), Extended data out dynamic random access memory (EDO-DRAM), static random access memory (SRAM), Flash memory as well as read-only memory (ROM).
OSC (14.318 Mhz)
PLL
CPUCLK
6-Stage Integer Pipeline
Instr. Cache RAM Data Cache RAM Branch Table RAM
Power Mang. Unit
3 Serial ICE Unit Serial ICE Bus
Timer (x2)
Internal Bus Interface Unit
32-bit CPU Internal Bus
32-bit Internal DMA bus
UART (x2)
PCI Bridge
Memory Controller
DMA Controller
Parallel Port Interface
Sync. Serial Port
PCI Bus
DRAM/Flash/ 8-bit-DMA/ ROM Port 16-bit-IO Bus
Fig 1-1 : W90220 Internal Block Diagram
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2. FEATURES
* PQFP 208-pin package * High level of integration * minimal number of inter-chip connections * 32-bit PA-RISC core with cache memory, multiply-accumulate module and flexible power management unit * DMA controller provides two external 8-bit DMA slots and four 16-bit IDE-IO slots * memory controller supports four banks of EDO- or fast-page-mode DRAM, Flash, ROM and SRAM * an PCI bridge supports four PCI master devices * an IEEE-1284 compliant parallel port connecting an external printer * two RS-232 compliant serial port connecting external MODEM controller or other serial devices * a synchronous serial port connecting external audio or telephony codec devices * two timer channels for general purpose usage * High performance and low power consumption * 0.35-micron single-poly-triple-metal CMOS process * split rail design (3.3V/5V IO and 3.3V core) * maximal operation frequency : 150 Mhz * typical active current : 2.5mA/Mhz * typical suspend current (PLL turn off) : * fully static design, afford dynamic turn on/off cpu clock or PLL module+ * programable standby clock to reduce standby current * real time clock and UART baud rate base on 14.318 Mhz * A flexible hardware serial ICE port for monitor/update cpu status at any time
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3. PIN CONFIGURATION
The W90220 family of embedded controllers is available in a 208-pin quad flat pack (PQFP) device configuration, shown below.
3.1. PIN DIAGRAM
N F A U L T N A U F D N I N I T D A C K 1 D A C K 0 DD V V RR DOSCCEEDDDDDDDDS DS S S SQQDDDDDDDDD pCp101001234567O V D II DTOO 5 CRW V0## D M A R D Y I N T D #
N S A EPC LEK
V D D p
B U S Y
N S T B
V S S p
V S S i
S V EEEEEEEEED LDDDDDDDDD O01234567i
V S S i
S Y N C
V S S p
S V CSDT LDDC KIp1
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 VSSi MD8 VSSp MD9 VDDp MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 VSSp MD20 MD21 VDDi MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 VDDp MD30 VSSp MD31 VSSi CAS0# VDDl PLLOSC VSSl CAS1# CAS2# CAS3# WE# DCD0# RI0# DSR0# CTS0# 1
1 5 0 160
1 4 0
1 3 0
1 2 0
1 1 0 100
170 90
180
W 90220F
(208-pin PQ F P )
80 70
190
200 60
1 0
2 0
3 0
4 0
5 0
INTC# INTB# INTA# PDA0 PDA1 PDA2 PDA3 VSSp PDA4 VSSi PDA5 PDA6 PDA7 COMBE0# PDA8 VDDp PDA9 PDA10 VSSp PDA11 PDA12 PDA13 PDA14 PDA15 COMBE1# PPAR# SERR# PERR# STOP# VDDi DEVSEL# VDDp TRDY# VSSp IRDY# FRAME# COMBE2# PDA16 PDA17 PDA18 PDA19 VSSi PDA20 VDDp PDA21 VSSp PDA22 PDA23 COMBE3# PDA24 PDA25 PDA26
S I N 0
S O U T 0
D T R 0 N
R T S 0 N
S O U T 1
S I N 1
P C I R S T
V D D p
P C I C L K
V S S p
R A S 0 #
V D D 5 V
R A S 1 #
R A S 2 #
R A S 3 #
R C S 0 #
R C S 1 #
R C S 2 #
RMM RMMM VMM V P CAAOAAADAASW S 0 1M2 3 4D5 6 SR 3 E i pO # N N
VM VMMMM R DASAAAAO D7 S 8 9 1 1M p i 01R W #
R O M O E #
G N T 0 #
G N T 1 #
P R E Q 0 #
P R E Q 1 #
P D A 3 1
P D A 3 0
P D A 2 9
V S S p
P D A 2 8
V D D p
P D A 2 7
W A K E U p
R E S U M E
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3.2 DETAILED PIN DESCRIPTIONS
The following abbreviations are used for pin types in the following sections : (I) indicates inputs; (O) indicates outputs; (I/O) indicates a bidirectional signal; (TS) indicates three-state; (OC) indicates open collector.
PIN Name CPU Signal PWRON PLLOSC OSC PCI LOCAL BUS INTA# INTB# INTC# INTD# PREQ0# PREQ1# GNT0# GNT1# PCIRST# PCICLK SERR#
DIR I I I
PIN # 30 199 132
DESCRIPTION CPU Power-On reset input, high active 14.318Mhz Oscillator input for internal PLL 14.318Mhz Oscillator input for Timer, UART
for more detail description of the PCI signals please refer to the PCI LOCAL BUS SPECIFICATION
I
I O O O I
102 103 104 105 42 43 40 41 7 9 78
PERR#
I/O
77
PCI Interrupt input, level senstive, low active signal. Once the INTx# signal is asserted, it remains asserted until the device driver clear the pending request. When the request is cleared, the device deasserts its INTx# signal. PCI Request input, indicates to the PCI arbiter that this agent desires use of the bus. PCI Grant output, indicates to the agent that access to the bus has been granted. PCI Reset output, is used to bring PCI-specific registers, sequencers, and signals to a consistent state. Low active. PCI Clock output, provides timing for all transactions on PCI and is an input to every PCI device. PCI System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. The assertion of SERR# is synchronous to the clock and meets the setup and hold times of all bused signals. PCI Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special Cycle. The PERR# pin is sustained tri-state and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected. The minimum duration of PERR# is one clock for each data phase that a data parity error is detected. An agent cannot report a PERR# until it has claimed the access by asserting DEVSEL# (for a target) and completed a data phase or is the master of the current transaction.
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PDA[31:0]
I/O
44-46, 48, 50, 53-55, 57, 58, 60, 62, 64-67, 81-85, 87, 88, 90, 92-94, 96, 98-101,
STOP# TRDY#
I/O I/O
76 72
DEVSEL#
I/O
74
C/BE[3:0]#
I/O
56,68,80,91
FRAME#
I/O
69
IRDY#
I/O
70
PCI tri-state Address/Data bus, Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. PCI supports both read and write bursts. The address phase is the clock cycle in which FRAME# is asserted. During the address phase PDA[31:0] contain a physical address. During data phases PDA[7:0] contain the least significant byte (lsb) and PDA[31:24] contain the most significant byte (msb). Write data is stable and valid when IRDY# is asserted and read data is stable and valid when TRDY# is asserted. Data is transferred during those clocks where both IRDY# and TRDY# are asserted. PCI Stop indicates the current target is requesting the master to stop the current transaction. PCI Target Ready indicates the selected device ability to complete the current data phase of the transaction. A data phase is completed on any clock both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that valid data is present on PDA[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. PCI Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. PCI Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE[0]# applies to byte 0 (lsb) and C/BE[3]# applies to byte 3 (msb). PCI Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAM# is deasserted, the transaction is in the final data phase or has completed. PCI Initiator Ready indicates the bus master ability to complete the current data phase of the transaction. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on PDA[31:0]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together.
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PPAR
I/O
79
PCI Parity is even parity across PDA[31:0] and C/BE[3:0]#. PPAR is stable and valid one clock after the address phase. For data phases, PPAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. (PPAR has the same timing as PDA[31:0], but it is delayed by one clock.) The mater drives PPAR for address and write data phases; the target drives PPAR for read data phase. DMA Request signals request an external transfer on DMA channel 0 (DREQ0) or DMA channel 1 (DREQ1). DMA Acknowledge signals acknowledge an external transfer on DMA channel 0 (DREQ0) or DMA channel 1 (DREQ1). DMA Device Ready signal is used to extend the length of DMA bus cycles. If a device wants to extend the DMA bus cycles, it will force the DMARDY signal low when it decodes its address and receives a IOR or IOW command. DMA Chip Select signals select the corresponding I/O devices for programming or DMA transfers. DMA I/O read signal is used to indicate to the I/O device that the present bus cycle is an I/O read cycle. DMA I/O write signal is used to indicate to the I/O device that the present bus cycle is an I/O write cycle. Terminal count for DMA channels, the pin is driven active for one clock when byte count reaches zero and after the last transfer for a DAM has completed. 8-bit DMA I/O Data bus, bit 0 is the most significant bit. For more detail description of the ECP interface signals, please refer to the IEEE P1284 Standard ECP busy input signal ECP fault input ECP acknowledge input ECP parity error ECP Select ECP select output ECP initialization ECP Autofeed ECP Strobe Bi-directional ECP Data bus, ED[0] is the most significant bit (msb). DRAM Row Address Strobe, Banks 0-1. These signals are used to select the DRAM row address. A High-to-Low transition on one of these signals causes a DRAM in the corresponding bank to latch the row address and begin an access.
DMA Interface DREQ0 DREQ1 DACK0 DACK1 DMARDY
I O I
127 128 134 135 106
CS0 CS1 IOR IOW TC0 TC1 DD[0:7] ECP Interface Busy nFault nAck PError Select nSelectIn nInit nAutoFd nStrobe ED[0:7]
O O O O
129 130 108 107 109 111 126-119
I/O
I I I I I O O O O I/O
151 153 154 155 156 145 147 148 150 144-137
Memory Controller Interface RAS#[0:1] O 11, 13
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RAS#[2:3]/ PREQ#[2:3]
I/O
14, 15
CAS#[0:3]
O
197, 201-203
WE# RCS#[0:1]
O O
204 16, 17
RCS#[2:3]/ GNT#[2:3]
O
18, 19
ROMEN
O
22
ROMRW# ROMOE# MA[0:11]/ DA[0:11]
O O O
38 39 20-21, 23-25, 27-28, 32, 3437
MD[0:7] MD[8:15]/ DD[8:15]
I/O I/O
157-164 166, 168, 170-175
MD[16:31]
I/O
176-179, 181,182,184191,193,195 1
If MD[20] is pull down, these pins serve RAS signals for external DRAM's bank 2 and 3. If MD[20] is pull high, these pins serve as "PCI Request 2 and 3" indicate to the PCI arbiter that the masters desires use of the bus DRAM Column Address Strobes, Byte 0-3. These signals are used to select the DRAM column address. A High-to-Low transition on these signals causes the DRAM selected by RAS#[0:3] to latch the column address and complete the access. DRAM Write Enable signal is used to write the selected DRAM bank. ROM Chip Selects, Banks 0-1. A low level on one of these signals selects the memory devices in the corresponding ROM bank. If MD[20] is pull down, these pins serve ROM "Chip select" for bank 2 and 3. If MD[20] is pull high, these pins serve as "PCI Grant 2 and 3" indicate to the PCI masters that access to the PCI bus has been granted. ROM Address Latch, ROM address are divided into two portions, higher address bits and lower address bits, the address will be put out on the MA bus in two consecutive cycles. The ROMEN signal is used to latch the higher address bits in the first ROM address cycle. FLASH ROM write enable. This signal is used to write data into the mrmory in a ROM bank (such as Flash ROM). ROM output enable. This signal enables the selected ROM Bank to drive the MD bus. Memory controller Memory Address bus. For DRAM access, MA[0:11] is the DRAM row address and the DRAM column address. For ROM/FLASH ROM access, MA[0:11] is the higher portion ROM space address bits in the first ROM address cycle, and the lower portion ROM space address bits after the first ROM address cycle. During DMA I/O cycles, these pins also serve as DMA address bus. MA[0] is the most significant bit (msb). Memory controller Data bus bit 0-7 for both DRAM data and ROM space data. Bit 0 is the most significant bit (msb). Memory controller Data bus bit 8-15for both DRAM data and ROM space data. During DMA cycles, these pins also serve as DMA data bus bit 8-15 for 16-bit DMA transfering. Bit 8 is the most significant bit (msb). Memory controller Data bus bit 16-31 for both DRAM data and ROM space data. Bit 16 is the most significant bit (msb).
COM1 Serial Port Signal SIN1 I
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COM1 serial data input from the communication link (modem or peripheral device).
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SOUT1
O
2 208 207 3 4 205 206 6 5
CTS1n I DSR1n I DTR1n O RTS1n O DCD1n I RIN1n I COM2 Serial Port Signal SIN2 I SOUT2 O
COM1 serial data output to the communication link (modem or peripheral device). COM1 clear to send signal COM1 data set ready COM1 data terminal ready COM1 request to send COM1 data carrier detect COM1 ring indicator COM2 serial data input from the communication link (modem or peripheral device). COM2 serial data output to the communication link (modem or peripheral device). Serial data-in from a external codec device Serial data-out to a exteral codec device Frame sync of SDI/SDO. This signal is an input signal during "slave mode" or output signal during "master mode" Serial Clock for SDI/SDO transfering. This signal is an input signal during "slave mode" or output signal during "master mode" If MD[24] is pull down, this pin serves as an external interrupt request. A active high-state in this pin will make EIER[12] be set. In this mode, this pin can also serve as an interrupt request pin for an IDE slot. If MD[24] is pull high, this pin serves a "resume" request to wake up the chip from "DOZE" mode. If MD[24] is pull down, this pin serves as an external interrupt request. A active high-state in this pin will make EIER[13] be set. In this mode, this pin can also serve as an interrupt request pin for an IDE slot. If MD[24] is pull high, this pin serves a "resume" request to wake up the chip from "SLEEP" mode. 5.0V Vdd (for a mixed 5.0V/3.3V enviornment) Global 3.3V Vdd
Synchronous Serial Port Signal SDI I 113 SDO O 118 SYNC I/O 116 SCLK I/O 114
Miscellaneous WAKEUP /INTR0
I
51
RESUME /INTR1
I
52
Power/Ground pin VDD5V I VDDp I
VDDi VDDl VSSl VSSi VSSp
I I I I I
12,110 8,31,49,61,73 ,89,112,133, 152,169,192 26,75,136,18 3 198 200 33,63,95,117, 146,165,196, 10,29,47,59, 71,86,97,115, 131,149,167, 180,194
3.3V Vdd (for internal logic only) 3.3V Vdd (for internal PLL logic) VSS (for internal PLL logic) VSS (for internal logic) Global VSS
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4 4.1
CPU CORE OVERVIEW
(Left for Blank)
4.2
BLOCK DIAGRAM
(Left for Blank)
4.3
FEATURES
* Base on PA-RISC 1.1 level-0 architecture * 32-bit integer instruction set and register files * Maximum 150Mhz operation frequency * 3.3V and 0.01W/Mhz at full speed operation * On-chip power management - Build-in software-independent dynamic power-down mode - Programable stand-by and sleep mode - Specific instruction to assist power-down control and ICE function * High-speed 32-bit integer pipeline design - 6 stages for Load/Store instructions - 5 stages for other instructions * On-chip cache memory - 4KB, direct-map instruction cache and 4KB, 4-way set-associative data cache - Write-through and write-back support for data cache - 1 level read buffer and wrap-arround support in each cache - l level write buffer and hit-under-miss support in data cache - Cache-locking support in instruction cache * Dynamic branch prediction
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- Build-in 1-level 256 entry, 4-way set-associative (LRU) Branch-Target-Buffer to improve branch prediction rate and accelerate pipeline throughput * Two high speed (12ns) 16-bit MACs (or one 32-bit MAC) and multimedia extended instructions have been built-in for DSP releated calculation * Specific serial-ICE-interface to facilitate chip debuging and software development
4.4
PA-RISC ARCHITECTURE
4.4.1 CPU RESOURCES
(Left for Blank)
4.4.2 ADDRESSING MODES & MEMORY MAP
(Left for Blank)
4.4.3 BRANCH CONTROL
(Left for Blank)
4.4.4 INTERRUPT CONTROL
(Left for Blank)
4.5
PIPELINE OPERATION
(Left for Blank)
4.6
IMPLEMENTATION DEPENDENT FEATURES
4.6.1 MULTIMEDIA ENTENSION INSTRUCTION SET
(Left for Blank)
4.6.2 MAC UNIT AND RELEATED INSTRUCTION SET
(Left for Blank)
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4.6.3 DIAGNOSTIC INSTRUCTION SET
(Left for Blank)
4.6.4 FLUSH INSTRUCTION/DATA CACHE & BTB
(Left for Blank)
4.6.5 LEVEL-0 DEBUG SFU
(Left for Blank)
4.7 POWER MANAGEMENT UNIT
(Left for Blank)
4.8 SP-ICE INTERFACE
(Left for Blank)
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5 5.1
MEGACELLS FUNCTIONAL DESCRIPTIONS MEMORY CONTROLLER
5.1.1
Overview : (Left for Blank) Block Diagram : (Left for Blank) Features : * supports up to 4 banks of FPM- (fast page mode) or EDO-DRAM (SIMM) * supports up to 4 banks of ROM or Flash memory * optional parity bits for each data bytes * CAS#-befor-RAS# refresh cycles for DRAM module * programmable RAS#/CAS# timing for DRAM access * programmable wait states for ROM and Flash memory access Related Pins : (Left for Blank) Operation Modes : (Left for Blank)
5.1.2
DMA CONTROLLER
Overview : (Left for Blank) Block Diagram : (Left for Blank) Features : * provides two channels for external devices to do 8-bit dma io-to-memory transfer * flexible block-transfer mode and demand mode are supported * provides two 16-bit IDE IO-channels connecting IDE devices * provides 8-bit io-to-memory or memory-to-io transfer mode * provides 8-, 16- and 32-bit memory-to-memory transfer modes
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* dma transfer between pci memory to/from system memory are also support * 4 words (16 bytes) memory burst-access; linear burst order * build-in 4-words data FIFO to accelerate memory access * the starting address of source and target shall be halfword boundary for 16-bit memory transfer and word boundary for 32-bit memory transfer Related Pins : There are 19 pins allocated for two external dma slots to do 8-bit io-to-memory dma transfer. These pins include 8bit bi-directional data bus as well as 11control/status pins. - DREQ0, DREQ1 (input) : Set high by external dma devices of slot 0 and slot 1 respectively to request dma 8-bit io-to-memory transfer. The DREQ(s) shall keep asserted (logic 1) during "demand mode" transfering, while during "block mode" transfering the DREQ(s) shall be deasserted (logic 0) after their corresponding DACK(s) is granted and before the end of dma block transfering. - DACK0, DACK1 (output) : Set high by the dma controller to acknowledge the dma DREQ(s) from dma slot 0 and slot1 respectively. Whenever DACK(s) is set high, the dma transfer is on-going. - TC0, TC1 (output) : At the end of the last byte of dma transfer, the TC(s) will be pulse high for 1 system clock immediately indicating that dma transfer is finished. - DMARDY (input) : This signal is used by external dma devices to insert wait states when the devices being progrmming by cpu. DMARDY is an open collector signal which shall be pull-up externally (default "don't insert any wait states"). If any devices need to lengthen the IOR or IOW cycle, it must drive DMARDY to logic high within one system clock after IOR or IOW signal being set high. - IOR (output) : This signal is pulsed high indicating an IO read command cycle is on-going whether in cpu mode (DACK(s) = 0s) or in dma mode (DACK(s) = 1). - IOW (output) : This signal is pulsed high indicating an IO write command cycle is on-going whether in cpu mode (DACK(s) = 0s) or in dma mode (DACK(s) = 1). - CS0, CS1 (output) : These two signals are Chip Selects of dma slot 0 and slot 1. As dma controller wants to programming dma devices, it must drive the corresponding CS(s) to logic high. - DD[0:7] (in/out) : Birdirectional 8-bit data bus with bit 0 is the most significant bit. Operation Modes : (Left for Blank)
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5.1.3
PCI BRIDGE
Overview : (Left for Blank) Block Diagram : (Left for Blank) Features : * supports "long framing" and "short framing" (synchronous, frame-based protocol) * provides "master mode" and "slave mode" * build-in two 48x16 (or 24x32) data fifo to accelerate transmit/receive operation * programable data bits per one frame (sampling rate) : 1 ~ 256 bits/frame * programable data bits per word (resolution of each sampling) : 1 ~ 32 bits/word * programable multi-word (per frame) transfer : 1 ~ 16 words/frame Related Pins : (Left for Blank) Operation Modes : (Left for Blank)
5.1.4
PARALLEL PORT INTERFACE
Overview : (Left for Blank) Block Diagram : (Left for Blank) Features : * supports all IEEE P1284 transfer modes including : - Compatible (centronic) mode (forward channel) - Nibble mode (reverse channel, compatible with all existing PC hosts - relies on software control) - Byte mode (reverse channel, compatible with IBM PS/2 host) - EPP mode (bi-directional half-duplex channel - relies on software control) - ECP mode (fast bi-directional half-duplex channel) * Host-side design * Provide a special operation mode to emulate peripheral-side centronic device * Build-in one 16bytes FIFO to accelerate ECP mode and centronic forward transfer * Provide DMA capability to accelerate moving data from parallel port interface to system memory * ECP mode is also including : - High performance half-duplex forward and reverse channel
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- Interlocked handshake, for fast reliable transfer - Forward "channel-addressing/command transfer" for low-cost peripherals - Support reverse RLE decompression - Peer-to-peer capability Related Pins : 17 pins are allocated for Parallel-Port-Interface including 8-bit data bus, 5 status input signals and 4 control output signals. - nStrobe (output) : Compatible Mode : Set active low to transfer data into peripheral device's input latch ECP Mode : Used in a closed-loop handshake with "Busy" to transfer data or address information from host to peripheral device. - nAutoFd (output) : Compatible Mode : Set low by host to put some printers into auto-line feed mode. May also be used as a ninth data, parity, or command/data control bit. ECP Mode : The host drives this signal for flow control in the reverse direction. It is used in an interlocked handshake with "nAck". "nAutoFd" also provides a ninth data bit used to determine whether command or data information is present on the data signals in the forward transfering. - nInit (output) : Compatible Mode : Pulsed low in conjunction with "nSelectIn" active low to reset the interface and force a return to compatible mode idle state. ECP Mode : This signal is driven low to place the channel in the reverse direction. While in this mode, the peripheral is only allowed to drive the bi-directional data signals when "nInit" is low and "nSelectIn" is high. - nSelectIn (output) : Compatible Mode : Set low by host to select peripheral device. ECP Mode : Driven high by host while in ECP mode. Set low by host to terminate ECP mode and return the link to the compatible mode. - nAck (input) : Compatible Mode : Pulse low by the peripheral device to acknowledge transfer of a data byte from the host. ECP Mode : Used in a close-loop handshake with "nAufoFd" to transfer data during reverse transfering. - Busy (input) : Compatible Mode : Driven high to indicate that the peripheral device is not ready to receive data. ECP Mode : The peripheral device uses this signal for flow control in the forward transfering. "Busy" also provides a ninth data bit used to determine whether command or data information is present on the data signals in the reverse direction. - PError (input) : Compatible Mode : Driven high to indicate that the peripheral device has encountered an error in its paper path (ex. paper empty). Peripherals shall set "nFault" low whenever they set "PError" high. ECP Mode : Peripherals drive this signal low to acknowledge "nInit". The host relies upon "PError" to deterine when it is permitted to drive the data signals.
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- Select (input) : Compatible Mode : Set high to indicate that the peripheral device is on-line. ECP Mode : Used by peripheral to reply to the requested extensibility byte sent by the host during the negotiation phase. - nFault (input) : Compatible Mode : Set low by peripheral device to indicate that an error has occured. ECP Mode : Set high to acknowledge 1284 compatibility during negotiation phase. During ECP mode the peripheral may drive this pin low to request communications with the host. This signal would be typically used to generate an interrupt to the host. This signal is valid in both forward and reverse trnasfers. - ED[0:7] (in/out) : 8-bit bus used to hold data, address or command information in all modes. The bit 0 is the most significant bit.
Operation Modes : (Left for Blank)
5.1.5
UART
Overview : The W90220 contains two Universal Asynchronous Receiver/Transmitter (UART) ports, one of them provides complete MODEM-control and serial transfermation capabilities, whereas the other one provides only serial transfermation capability. The UART performs serial-to-parallel conversion on data characters received from a peripheral device such as MODEM, and parallel-to-serial conversion on data characters received from the CPU. One 16 bytes transmitter FIFO (TX-FIFO) and one 16 bytes (plus 3 bits of error data per byte) receiver FIFO (RXFIFO) have been built in to reduce the number of interrupts presented to the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status reported includes error conditions (parity, overrun, framing, or break interrupt) and states of TX-FIFO and RX-FIFO. Block Diagram :
32-bit CPU bus
8 8 8
RTS# TX-FIFO (16x8) & Control Baud Rate Generator TX shift register RX shift register Modem Status Reg RX-FIFO (16x8) & Control Modem Control Reg DTR# OUT1# OUT2# CTS# DSR# DCD# RI#
SDO
OSC (14.318Mhz)
SDI
Fig 5.1.5-1 UART Block Diagram
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Features : * transmitter and receiver are each buffered with 16 bytes FIFO's to reduce the number of interrupts presented to the CPU * MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD) * Fully programmable serial-interface characteristics : -- 5-, 6-, 7-, or 8-bit characters -- even, odd, or no-parity bit generation and detection -- 1-, 1&1/2, or 2-stop bit generation -- baud rate generation * line break generation and detection * false start bit detection * full prioritize interrupt system controls * loop back mode for internal diagnostic testing Related Pins : (COM1) - SIN1 (input) - SOUT1 (output) - CTS1# (input) - DSR1# (output) - DTR1# (input) - RTS1# (output) - DCD1# (input) - RI1# (output)
: Serial data input from peripheral device or MODEM : Serial data output to peripheral device or MODEM : Clear to send signal : Data set ready : Data terminal ready : Request to send : Data carrier detect : Ring indciator
(COM2) - SIN2 (input) : Serial data input from peripheral device or MODEM - SOUT2 (output) : Serial data output to peripheral device or MODEM Operation Modes : - Interrupt Mode operation : A. Receiver control : - Set FCR[0:1] to select a proper receiver threshold level and then turn on "receiver data available interrupt" (Irpt_RDA) by set IER[7] to logic 1. - The Irpt_RDA will be triggered when the receiver FIFO (RX-FIFO) has reached its programmed trigger level, and it will be cleared as the available data in RX-FIFO drops below the trigger level. - As Irpt_RDA occured, the corresponding IIR bits will be set to inform the software application that data in RX-FIFO has reached programmed threshold level. - If the received data has any errors, the "line status interrupt" (Irpt_RLS) will occur and has higher priority than Irpt_RDA. - If "time out interrupt" (Irpt_TOR) is enable by set IER[7] and TOR[0] to logic 1s. The Irpt_TOR will occur, if the following conditions exist : - at least one character is in RX-FIFO. - RX-FIFO is not received any data or accessed by CPU from the most recent serial character received, and the time period, counting by baud rate bit clock, has exceeded the value being programmed in TOR[1:7]. - The Irpt_TOR and the time-out counter will be cleared as the CPU reads one character from RX-FIFO. - The time-out counter is reset after a new character is received or after the CPU reads the RX-FIFO.
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B. Transmitter control : - Set IER[6] to logic 1 to enable "transmitter empty interrupt" (Irpt_THRE) before transmitter operation. - Once the transmitter FIFO (TX-FIFO) is empty, the Irpt_THRE is triggered and the corresponding IIR bits are set to inform the CPU to fill the TX-FIFO (maximum 16 bytes of characters). - The Irpt_THRE is reset after the CPU reads the IIR (IIR[4:7] must be 4'b0010 at that time) or writes a character into TX-FIFO. - Irpt_RDA and Irpt_TOUT has the same interrupt priority (2nd priority) while Irpt_THRE has a lower priority (3rd priority). - Polled Mode operation : (refer to "LSR" register discriptions located on Section 5.2.5) - No interrupts need be enabled at this mode, the CPU always polls the LSR to check COM port status before taking any actions. - LSR[7] will be set as long as there is at least one byte in the RX-FIFO, and it is cleared if the RX-FIFO is empty. - LSR[3:6] will specify error(s) status which is handled the same way as in the interrupt mode operation, the IIR[4:7] is not affected since no interrupt is enabled. - LSR[2] will indicate when the TX-FIFO is empty. - LSR[1] will indicate that both TX-FIFO and shift register are empty. - LSR[0] will indicate whether there are any errors in the RX-FIFO.
5.1.6
SYNCHRONOUS SERIAL INTERFACE (SSI)
Overview : The SSI module within W90220 contains holding registers, shift registers, and other logic to support a variety of serial data communications protocols and provide a direct connection to external audio/telephony codec devices. Two 48 halfwords fifos, the transmitter fifo and receiver fifo, have been implented to accelerate both transmittion and receiving operations. These two fifos can be configured as 48 halfwords or 24 words depth depending on the data word length. Block Diagram :
32-bit CPU bus
16/32
16/32
TX-FIFO (48x16/24x32)
FIFO Control Logic
RX-FIFO (48x16/24x32)
16/32
16/32
32-bit TX-Shift reg
SCLK/SYNC & Shift-in/out control
32-bit RX-Shift reg
SDO
SYNC
SCLK
SDI
Fig 5.1.6-1 SSI Block Diagram
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Features : * supports "long framing" and "short framing" (synchronous, frame-based protocol) * provides "master mode" and "slave mode" * build-in two 48x16 (or 24x32) data fifo to accelerate transmit/receive operation * programable data bits per one frame (sampling rate) : 1 ~ 256 bits/frame * programable data bits per word (resolution of each sampling) : 1 ~ 32 bits/word * programable multi-word (per frame) transfer : 1 ~ 16 words/frame Related Pins : - SDI (input) : This pin contains the input data shifted from external audio/telephony codec devices - SDO (output) : This pin contains the output data shifted to external audio/telephony codec devices - SYNC (in/out) : This pin is the frame synchronization signal between SSI and codec devices. The SYNC may be input or output depending on SSI operated in slave- or master-mode respectively. - SCLK (in/out) : This pin is the serial bit clock between SSI and codec devices. Likewise, The SCLK may be input or output depending on SSI operated in slave- or master-mode respectively. Operation Modes : - Master Mode : Once CFGH[2] is set to logic 1 and MD[25] is pull high, SSI is operated in master mode, and the SYNC (determines the sampling rate) and SCLK is drived by SSI module to external codec devices. SCLK frequence = EXTCLK/[2*(CFGL[8:15] + 1)] SYNC period = SCLK * (CFGL[0:7] + 1) (5.1.6a) (5.1.6b)
- Slave Mode : Once CFGH[2] is set to logic 0 and MD[25] is pull down, SSI is operated in slave mode, the SCLK and SYNC are drived externally (may be from codec devices). So the sampling rate and SCLK frequence are determined by external devices, however software driver still need to properly set "serial data bit length" (CFGH[8:10] ) as well as "data words per frame" ( CFGH[12:15] ) to make SSI module working correctly. - Loop mode : This mode (CFGH[1] =1) aims at selftesting. When this bit is set, serial data-out "SDO" is connected to serial data-in "SDI" internally and SDO pin fixed at logic 0 state. Besides, if Loop and Master mode are chose concurrently, SSI module will not issue SYNC until TX-FIFO contains at least one data word. - Long Framing : When CFGH[3] is set to logic 1, SSI is operated in long framing mode. The following features are included in long framing mode : consists of the following features. - The SSI module always samples receive date (SDI) on the falling edge of SCLK, whereas always pushes transmit data (SDO) on the rising edge of SCLK. - The frame sync (SYNC) is asserted immediately as the first bit of transmit and receive data. - The frame sync (SYNC) is asserted for one "serial word length" which determined by CFGH[8:11]. Serial word length = CFGH[8:11] + 1 (5.1.6c) - The frame sync rate (sampling rate) and SCLK frequence follow eq (5.1.6b) and (5.1.6a) respectively on master mode and determined by external devices on slave mode. - The transmit FIFO and receive FIFO is configued as 48x16 if "serial word length" <= 16, and will be configured as 24x32 if "serial word length" > 16.
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- The shifting data bits on SDI and SDO are always MSB first. - If serial word length is not 16 or 32, it is software responsibility to left(MSB) justify the transmit data words before writing it to transmit FIFO, the received data before being written into receive FIFO is righ(LSB) justified automatically by SSI module where the unfilled MSBs are catneted with logic 0s. - SSI module always shifts out logic 0s on each frame sync if transmit FIFO is empty at that time. - A receiver FIFO interrupt will be asserted (when RX-FIFO interrupt is enable) if the received data words exceeds the receive FIFO's threshold level. Likewise, a transmitter FIFO interrupt will be asserted (when TX-FIFO interrupt is enable) if the available data words in transmit FIFO is lower than its threshold level. - Fig 6.1.5-2 shows a standard long framing transfer where serial word length is 3 (CFGH[8:11] = 2), words per frame is 3 (CFGH[12:15]=2) and bits per frame is 9 (CFGL[0:7] = 10).
SCLK SYNC SDI SDO
D1_1 D1_1 D1_2 D1_2 D1_3 D1_3 D2_1 D2_1 D2_2 D2_2 D2_3 D2_3 D3_1 D3_1 D3_2 D3_2 D3_3 D3_3 D1_1 D1_1 D1_2 D1_2
Fig 5.1.6-2 SSI long framing transfer
- Short Framing : When CFGH[3] is set to logic 0, SSI is operated in long framing mode. The following features are included in short framing mode consists of the following features. - The frame sync (SYNC) is asserted for one SCLK immediately before the first bit of transmit and receive data. - The frame sync (SYNC) is asserted for one SCLK period. - All other features are the same as long framing mode. - Fig 6.1.5-3 shows a standard short framing transfer where serial word length is 3 (CFGH[8:11] = 2), words per frame is 3 (CFGH[12:15]=2) and bits per frame is 9 (CFGL[0:7] = 10).
SCLK SYNC SDI SDO
D1_1 D1_1 D1_2 D1_2 D1_3 D1_3 D2_1 D2_1 D2_2 D2_2 D2_3 D2_3 D3_1 D3_1 D3_2 D3_2 D3_3 D3_3 D1_1 D1_1 D1_2 D1_2
Fig 5.1.6-3 SSI short framing transfer
5.1.7
TIMER CHANNELS
Overview : (Left for Blank)
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Block Diagram : (Left for Blank) Features : * Two 24-bit decremental timer channels with individual interrupt requests * Programmable timer clocks for each channels, the clock range is OSC ~ OSC/8'hFF * maximum uninterrupted time or timeout = 5 minutes (if OSC = 14.318Mhz) * Typical OSC frequence is 14.318Mhz. Related Pins : (None) Operation Modes : (Left for Blank)
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5.2 5.2.1
REGISTER DEFINITIONS MEMORY CONTROLLER REGISTERS
There are 24 8-bit registers included in the memory (ROM/DRAM) controller. Access to these registers are through a 8-bit "index" port and a 8-bit data port. The index port address is 0xf0000022 and the data port address is 0xf0000023. The memory controller supports ROM, Flash, EDO- and Fast-page-mode DRAM.
Table 5.2.1-1 : MEMC Register Map Index 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b
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(IO base (BA) : 0xf0000000) Description ROM bank 0 base register [0:7] ROM bank 0 base register [8:15] ROM bank 1 base register [0:7] ROM bank 1 base register [8:15] ROM bank 2 base register [0:7] ROM bank 2 base register [8:15] ROM bank 3 base register [0:7] ROM bank 3 base register [8:15] ROM Configuration register 0 [0:7] ROM Configuration register 1 [0:7] ROM Configuration register 2 [0:7] ROM Configuration register 3 [0:7] RAM bank 0 base register [0:7] RAM bank 0 base register [8:15] RAM bank 1 base register [0:7] RAM bank 1 base register [8:15] RAM bank 2 base register [0:7] RAM bank 2 base register [8:15] RAM bank 3 base register [0:7] RAM bank 3 base register [8:15] RAM Configuration register 0 [0:7] RAM Configuration register 1 [0:7] RAM Configuration register 2 [0:7] RAM Configuration register 3 [0:7]
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Symbol
Access R/W R/W R/W R/W R/W R/W R/W R/W
ROMconf0 ROMconf1 ROMconf2 ROMconf3
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
RAMconf0 RAMconf1 RAMconf2 RAMconf3
R/W R/W R/W R/W
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ROM Base Address Register ( ) Index : 0x00,0x02,0x04, 0x06 Read/Write Power-on Default : --
0
1
2
3
4
5
6
7
ROM base address bit 0-7 (most significant bits)
Index : 0x01,0x03,0x05,0x07
Read/Write
Power-on Default : --
0
1
2
3
4
5
6
7
ROM base address bit 8-15 These eight 8-bit registers (boundle to four 16-bit registers) defines the most significant 16 bits of each ROM banks' base (bottom) address. The "ROM base address" togather with the "ROM size" (defined in ROMconf0) construct the whole address range of each ROM banks. These ROM base registers do not contain any initial value after system power-on. All ROM access will be directed to bank 0 right after system power-on (for ROMconf3[3]=1 at that time). System programmer shall not set ROMconf3[3] to logic 0 before all ROM base and configuration registers have been filled with valid data.
ROM Configuration_0 Register (ROMconf0) Index : 0x08 Read/Write Power-on Default : 0x0
0 ROMen0 Bit 0
1
2 ROM bank_0 size
3
4 ROMen1
5
6 ROM bank_1 size
7
Enable ROM bank 0 0 = Disable 1 = Enable
Bits 1-3 Size of ROM bank 0
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ROMconf0[1:3] 000 001 010 011 100 101 110 111
ROM size (*Basic unit) 64K 128K 256K 512K 1M 2M 4M 16M
( "*Basic unit" may be "byte", "halfword" or "word" which is defined in ROMconf2[0:7] ) Bit 4 Enable ROM bank 1 0 = Disable 1 = Enable Bits 5-7 Size of ROM bank 1 (The definition is the same as ROMconf0[1:3])
ROM Configuration_1 Register (ROMconf1) Index : 0x09 Read/Write Power-on Default : 0x0
0 ROMen2 Bit 0
1
2 ROM bank_2 size
3
4 ROMen3
5
6 ROM bank_3 size
7
Enable ROM bank 2 0 = Disable 1 = Enable
Bits 1-3 Size of ROM bank 2 (The definition is the same as ROMconf0[1:3]) Bit 4 Enable ROM bank 3 0 = Disable 1 = Enable
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Bits 5-7 Size of ROM bank 3 (The definition is the same as ROMconf0[1:3])
ROM Configuration_2 Register (ROMconf2) Index : 0x0a Read/write Power-on Default : *note
0
1
2
3
4
5
6
7
ROM3DW
ROM2DW
ROM1DW
ROM0DW
Bits 0-1 Data Width of ROM bank 3 ROMconf2[0:1] 00 01 10 11 Data width Byte Halfword Word (reserved)
Bits 2-3 Data Width of ROM bank 2 (The definition is the same as ROMconf2[0:1]) Bits 4-5 Data Width of ROM bank 1 (The definition is the same as ROMconf2[0:1]) Bits 6-7 Data Width of ROM bank 0 (The definition is the same as ROMconf2[0:1]) *note : The default value of this register is determined by MD[30:31]. The states of MD[30:31] will be copied into ROMconf2[0:1]/[2:3]/4:5]/[6:7] during system power-on (cold) reset.
ROM Configuration_3 Register (ROMconf3) Index : 0x0b Read/write Power-on Default : 0b'11011xx
0
1 ROM Read Wait state
2
3 BK0only
4 LA
5
6 Reserved
7
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Bits 0-2 Wait states of ROM Read cycle ROMconf2[0:2] 000 001 010 011 100 101 110 111 Wait States 2 3 4 5 6 7 8 9
Only ROM read cycles have a programmable wait states, while Flash ROM write cycles are always 9-wait states. The AC timing of the ROM read/write cycles with different wait states are shown in AC timing specification. Bits 3 ROM Bank 0 Only When this bit is set, all ROM cycles will be directed to bank 0 despite of the programming value of Base, ROMconf0 and ROMconf1 registers. Logic Analyzer Mode Enable This mode is used for chip's testing and debugging. When this bit is set, some of the DMA pins are used to echo internal 486 bus' control/status signals. DACK0 echos ADS#; IOR echos BLAST#; DACK1 echos MIO# IOW echos BRDY# CS0 echos DC#; TC0 echos RDY#; CS1 echos WR#; TC1 echos HLDA
Bits 4
RAM Base Address Register ( ) Index : 0x20,0x22,0x24, 0x26 Read/Write Power-on Default : --
0
1
2
3
4
5
6
7
RAM base address bit 0-7 (most significant bits)
Index : 0x21,0x23,0x25,0x27
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Read/Write
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0
1
2
3
4
5
6
7
RAM base address bit 8-15 These eight 8-bit registers (boundle to four 16-bit registers) defines the most significant 16 bits of each RAM banks' base (bottom) address. The "RAM base address" togather with the "RAM size" (defined in ROMconf0) construct the whole address range of each RAM banks. The base address of all four DRAM banks have no default value after power-on reset. It is software's responsibility to well program these registers before access system DRAM.
RAM Configuration_0 Register (RAMconf0) Index : 0x28 Read/Write Power-on Default : 0x0
0 RAMTP3
1
2 RAMTP2
3
4 RAMTP1
5
6 RAMTP0
7
Bits 0-1 DRAM Bank 3's RAM type & Bank-size RAMconf0[0:1] 00 01 10 11 RAM type & Bank size (x32) 256K 1M 4M 16M
The following table defines how CPU address bus map to DRAM address : 256K ROW MA11 MA10 MA9 MA8 MA7 MA6
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1M ROW
*(A6) *(A8)
4M ROW
*(A6)
16M ROW A6 A8 A10 A11 A9 A7 COL A18 A19 A20 A29 A28 A27
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COL
*(A18) *(A19) *(A20)
COL
*(A18) *(A19)
COL
*(A18)
*(A6) *(A8) *(A10)
A8 A10 A11 A9 A18
A19 A20 A29 A28 A27
A10 A11 A19 A18
A20 A29 A28 A27
A20 A19 A18
A29 A28 A27
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MA5 MA4 MA3 MA2 MA1 MA0
A17 A16 A15 A14 A13 A12
A26 A25 A24 A23 A22 A21
A17 A16 A15 A14 A13 A12
A26 A25 A24 A23 A22 A21
A17 A16 A15 A14 A13 A12
A26 A25 A24 A23 A22 A21
A17 A16 A15 A14 A13 A12
A26 A25 A24 A23 A22 A21
Bank Selector 2 Banks 4 Banks A11 A10, A11
Bank Selector A9 A8, A9
Bank Selector A7 A6, A7
Bank Selector A5 A4, A5
Note * : Don't care pins (only for testing issue). ** : A0 is MSB and A31is LSB. Bits 2-3 DRAM Bank 2's RAM type & Bank-size (The definition is the same as RAMconf0[0:1]) Bits 4-5 DRAM Bank 1's RAM type & Bank-size (The definition is the same as RAMconf0[0:1]) Bits 6-7 DRAM Bank 0's RAM type & Bank-size (The definition is the same as RAMconf0[0:1])
RAM Configuration_1 Register (RAMconf1) Index : 0x29 Read/Write Power-on Default : 0x0
0 PAREN Bit 0
1 RAMen3
2 RAMen2
3 RAMen1
4 RAMen0
5 DIS384K
6 FW
7 FR
Enable parity-check of memory data bus 0 = Disable parity check 1 = Enable parity check
Bit 1
DRAM bank_3 enable 0 = Disable 1 = Enable
Bit 2
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DRAM bank_2 enable
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0 = Disable 1 = Enable Bit 3 DRAM bank_1 enable 0 = Disable 1 = Enable Bit 4 DRAM bank_0 enable 0 = Disable 1 = Enable Bit 5 Swap out 0xA0000 ~ 0xFFFFF When this bit is set to a logic 1, address space 0xA0000 ~ 0xFFFFF will not be recognized as "system" DRAM space. Fast Write Enable (FW) "FW" together with RAMconf2[2:3] ("CASPC, CASWR") determine CAS# precharge- and active-time during "DRAM write" cycles. (Table 5.2.1-2 CAS# precharge-time during "write cycle") FW, CASPC 10 11 00 01 CAS# precharge-time (SYSCLK) 0.5 0.5 1 2
Bit 6
(Table 5.2.1-3. CAS# active-time during "write cycle") FW, CASWR 10 11 00 01 Bit 7 CAS# active-time (SYSCLK) 0.5 1.5 1 2
Fast Read Enable (FR) "FR" together with RAMconf2[2] ("CASPC") and RAMconf3[6:7] ("CASRD[0:1]") determine CAS# precharge- and active-time during "DRAM read" cycles.
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(Table 5.2.1-4. CAS# precharge-time during "read cycle") FR, CASPC 10 11 00 01 CAS# precharge-time (SYSCLK) 0.5 0.5 1 2
(Table 5.2.1-5. CAS# active-time during "read cycle") FW, CASRD[0:1] 100 101 110 111 000 001 010 011 CAS# active-time (SYSCLK) 0.5 1.5 2.5 3.5 1 2 3 4
RAM Configuration_2 Register (RAMconf2) Index : 0x2a Read/Write Power-on Default : 0x15
0
1
2 CASPC
3 CASWR
4
5
6
7
RASPC[0:1]
R2CRD[0:1]
R2CWR[0:1]
Bits 0-1 RAS# precharge time (RASPC[0:1]) "RASPC[0:1]" determine RAS# precharge-time during every "DRAM " cycles. (Table 5.2.1-6. RAS# precharge-time during "DRAM cycle") RASPC[0:1] 00 01 10 11
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RAS# precharge-time (SYSCLK) 2 3 4 5
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W90220F
Bits 2
CAS# precharge time (CASPC) This bit together with RAMconf1[6:7] ("FW, FR") determine CAS# precharge-time during "DRAM write or read" cycles respectively. Please refer Table 5.2.1-2 and Table 5.2.1-4 to get detail information. CAS# active time during DRAM-write (CASWR) This bit together with RAMconf1[6] ("FW ") determine CAS# active-time during "DRAM write" cycles. Please refer Table 5.2.1-3 to get detail information.
Bits 3
Bits 4-5 RAS# to CAS# delay time during DRAM-read cycles (R2CRD[0:1]) "R2CRD[0:1]" determine RAS# to CAS# delay during "DRAM-read" cycles if bank or page is changing at that time. (Table 5.2.1-7 RAS# to CAS# delay during "read cycle") R2CRD[0:1] 00 01 10 11 RAS# to CAS# delay (SYSCLK) 1 2 3 4
Bits 6-7 RAS# to CAS# delay time during DRAM-write cycles (R2CWR[0:1]) "R2CWR[0:1]" determine RAS# to CAS# delay during "DRAM-write" cycles if bank or page is changing at that time. (Table 5.2.1-8. RAS# to CAS# delay during "write cycle") R2CWR[0:1] 00 01 10 11 RAS# to CAS# delay (SYSCLK) 1 2 3 4
RAM Configuration_3 Register (RAMconf3) Index : 0x2b Read/Write Power-on Default : 0x09
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W90220F
0
1
2 CD2RD
3
4
5 CA2RA
6
7
REFRAT[0:1]
RA2CD[0:1]
CASRD[0:1]
Bits 0-1 Refresh Rate (REFRAT[0:1]) REFRAT[0:1] determine the frequence of DRAM refresh cycles. (Table 5.2.1-9 The frequence of DRAM refresh cycles) REFRAT[0:1] 00 01 10 11 Bit 2 Frequence of refresh cycle (us) 15 60 240 960
CAS# deassertion to RAS# deassertion (CD2RD) 0 = The delay time for CAS# deassertion to RAS# deassertion is 1 SYSCLK for CAS-before-RAS refresh cycle. 1 = The delay time for CAS# deassertion to RAS# deassertion is 2 SYSCLK for CAS-before-RAS refresh cycle.
Bits 3-4 RAS# assertion to CAS# deassertion (RA2CD[0:1]) These two bits determine the duration between RAS# assertion to CAS# deassertion for CASbefore-RAS refresh cycle. (Table 5.2.1-10 Delay time from RAS# assertion to CAS# deassertion) RA2CD[0:1] 00 01 10 11 Bit 5 Delay (SYSCLK) 1 2 3 4
CAS# assertion to RAS# assertion (CA2RA) 0 = The delay time for CAS# assertion to RAS# assertion is 1 SYSCLK for CAS-before-RAS refresh cycle. 1 = The delay time for CAS# assertion to RAS# assertion is 2 SYSCLK for CAS-before-RAS refresh cycle.
Bits 6-7 CAS# active time during DRAM-read (CASRD[0:1])
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W90220F
These two bits together with RAMconf1[7] ("FR ") determine CAS# active-time during "DRAM read" cycles. Please refer Table 5.2.1-5 to get detail information.
5.2.2 DMA REGISTERS
There are twelve registers included in two channels Direct Memory Access (DMA) controller. The IO address map is allocated from 0xf0000200 to 0xf000022c. Table 5.2.2-1 : DMA Register Map Port Addr. BA + 0x200 BA + 0x204 BA + 0x208 BA + 0x20c BA + 0x210 BA + 0x214 BA + 0x218 BA+ 0x21c BA + 0x220 BA + 0x224 BA + 0x228 BA + 0x22c Symbol SAR0 TAR0 LETH0 MOD0 SAR1 TAR1 LETH1 MOD1 DBA0 DBA1 LCAR0 LCAR1 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Description Channel 0 Source Address Register Channel 0 Target Address Register Channel 0 Length Register Channel 0 Mode Control Register Channel 1 Source Address Register Channel 1 Target Address Register Channel 1 Length Register Channel 1 Mode Control Register DMA IO Device 0 Bass Address DMA IO Device 1 Base Address Channel 0 Length Counter Channel 1 Length Counter (IO base (BA) : 0xf0000000)
Source Addrsee Register (SAR0 and SAR1) Port address : 0xf0000200 Port address : 0xf0000210 Read/Write Read/Write Power-on Default : 0x00000000 Power-on Default : 0x00000000
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W90220F
0
1
2
3
4
5
6
7
Source Address Register byte 0
8
9
10
11
12
13
14
15
Source Address Register byte 1
16
17
18
19
20
21
22
23
Source Address Register byte 2
24
24
26
27
28
29
30
31
Source Address Register byte 3 Bit 0-31 Source address register(SAR) Define DMA transfer source address. In memory to memory mode, the source address should be set in word boundary.
Target Address Register (TAR0 and TAR1) Port address : 0xf0000204 Port address : 0xf0000214 Read/Write Read/Write Power-on Default : 0x00000000 Power-on Default : 0x00000000
0
1
2
3
4
5
6
7
Target Address Register byte 0
8
9
10
11
12
13
14
15
Target Address Register byte 1
16
17
18
19
20
21
22
23
Target Address Register byte 2
24
24
26
27
28
29
30
31
Target Address Register byte 3 Bit 0-31 DMA target address register(TAR) Define target address. In memory to memory mode, the target address should be set in word
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W90220F
boundary.
Length Register (LETH0 and LETH1) Port address : 0xf0000208 Port address : 0xf0000218 Read/write Read/write Power-on Default : 0x00000000 Power-on Default : 0x00000000
0
1
2
3 Reserved
4
5
6
7
8
9
10
11 Reserved
12
12
14
15 LEN0
16
17
18
19 LEN1-8
20
21
22
23
24
24
26
27
28 LEN9-16
29
30
31
Bit 0-14 Reserved Bit 15-31 Transfer Length (LEN)
LEN 0-16 indicate DMA transfer length with max 128k-byte transferring. In memory to memory tranfser mode, the length must in word boundary, because of vounting by word in length counter.
Mode Control Register (MOD0 and MOD1) Port address : 0xf000020c Port address : 0xf000020c Read/Write Read/Write Power-on Default : 0x0000000f Power-on Default : 0x00000000
0 DMAen
1 Reserved
2 TCIen
3 ECPen
4 TC
5 M2M
6 DEM
7 IOtype0
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W90220F
8 IOtype1
9 TRtype
10
11
12
13 IOrec
14
15
16
17
18 Wstate Wsate
19
20
21 FIX
22 Reserved
23 Tout0 CS0L (MOD0) (MOD1)
DACK0L DACK1L
24
25
26
27 Tout1-8
28
29
30
31 (MOD0)
CS1L
DACK1A
TO0
TO1
Reserved
(MOD1)
Bit 0
DMA enable(DMAen) 1 = DMA transfer enable. 0 = DMA transfer disable
Bit 1
Reserved Set to 0
Bit 2
Terninal count interrupt enable(TCIen) 1 = enable terminal count interrupt Once this bit is set, and TC is asserted, the DMAC will generate external interrupt to host. Enable ECP as DMA device(ECPen) 1 = ECP is set as DMA device
Bit 3
Bit 4
Terminal count flag(TC) 1 = indicate the length counter reaches 0, and theTC asserted
Bit 5
Memory to memory transfer(M2M) 1 = DMA is set to memory to memory transfer 0 = DMA memory to memory transfer is disable
Bit 6
Demand mode or block mode select(DEM) 1 = DMA transfer between memory and IO is demand mode 0 = DMA transfer between memory and IO is block mode
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W90220F
This bit is valid only in the transfer between memory and IO. Bit 7-8 DMA IO device type(IOtype) 00 = 8-bit type, length counter(LENC) counts by byte 01 = 16-bit type, length counter counts by half word 10 = 32-bit type, length counter countes by word 11 = undefined Only 8-bit external IO device is supported. Bit 9-10 DMA transfer type(TRtype) 00 = memory to memory transfer 01 = memory to IO transfer 1x = IO to memory transfer Bit 11-15 DMA IO read/write command recovery time(IOrec) This field define the recovery cycle between two read/write command. Bit 16-20 DMA IO read/write command wait state(Wstate) This field define the IO read/write command wait state. In MOD0: Bit21 DMA transfer fix mode(FIX) 1 = Set DMA transfer as rotate mode. In rotate mode, the DMA controller acknowledge channel 1 request right after channel 0 being served. The channel 1 and channel 0 are served by turns. 0 = DMA is set in fix mode. Channel 0 is the most privilege. The channel 1 will not get the service token, unless channel 0 release the request. Bit22 Reserved This bit should be set to 0. Bit23-31 Ready timeout counter(Tout) Set IO device assert NOT ready timeout cycle count. When IO read/write command is issued, and if the IO device inserts wait state by asserting IORDY, the ready timeout counter starts to count. If the counter reach the Tout before read/write command is completed, the timeout flag TO0 or TO1 is to be set.
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W90220F
In MOD1: Bit 21 Set DACK0 low active(DACK0L) 1 = set DMA acknowledge signal DACK0 to low active 0 = set DMA acknowledge signal DACK0 to high active Bit 22 Set DACK1 low active(DACK1L) 1 = set DMA acknowledge signal DACK1 to low active 0 = set DMA acknowledge signal DACK1 to high active Bit 23 Set CS0 low active(CS0L) 1 = Set IO device chip select CS0 to low active 0 = Set IO device chip select CS0 to high active Bit 24 Set CS1 low active(CS1L) 1 = Set IO device chip select CS1 to low active 0 = Set IO device chip select CS1 to high active Bit 25 DACK1 active 1 = indicate DMA channel 1 acknoewledge DACK1 is active Bit 26 Channel 0 time out(TO0) 1 = indicate channel 0 IORDY signal timeout This bit is read ONLY. Bit 27 Channel 0 time out(TO1) 1 = indicate channel 1 IORDY signal timeout This bit is read ONLY. Bit28-31 Reserved
DMA IO Device Bass Address (DBA0 and DBA1) Port address : 0xf0000220 Port address : 0xf0000224
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Read/write Read/write
Power-on Default : 0xfffff000 Power-on Default : 0xfffff000
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W90220F
0
1
2
3 DBA0-7
4
5
6
7
8
9
10
11
12
12
14
15
DBA8-15
16
17
18
19
20
21 Reserved
22
23
DBA16-19
24
24
26
27 Reserved
28
29
30
31
Bit0-19 DMA IO device base address(DBA) Define DMA device IO base. The base address should not conflict to internal mega cell base, and the bit0-3 should be always set to 0. Bit 20-31 Reserved
Length Counter Register (LCAR0 and LCAR1) Port address : 0xf0000228 Port address : 0xf000022c Read only Read only Power-on Default : --Power-on Default : ---
0
1
2
3 Reserved
4
5
6
7
8
9
10
11 Reserved
12
12
14
15 LENC0
16
17
18
19
20
21
22
23
LENC1-8
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W90220F
24
24
26
27
28
29
30
31
LENC9-16
Bit 0-14 Reserved
Bit 15-31 Length counter indicates the remainder to be transfer. DMA transfered number = Length Register LENC. TC is asserted by Length counter reaching 0. Reading Length Counter may not get the valid value if the channel is active, for the length may be in transition.
5.2.3
PCI BRIDGE INTERFACE REGISTERS
There are four 32 bits registers included in the PCI Bridge Interface controller. The IO address map is allocated from 0xf0000250 to 0xf000025c. Table 5.2.3-1 : PCI Bridge Register Map Port Addr. BA + 0x250 BA + 0x254 BA + 0x258 BA + 0x25c Symbol REG0 REG1 REG2 REG3 Access R/W R/W R/W R/W Description Master 0 Latency Register Master 1 Latency Register Master 2 Latency Register Master 3 Latency Register (IO base (BA) : 0xf0000000)
Master 0 Latency Register (REG0) Port address : 0xf0000250 Read/Write Power-on Default : 0x000003ff
0
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1
2
3
4
5
6
7
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W90220F
Reserved
8
9
10
11 Reserved
12
13
14
15
16 PERRen
17 SERRen
18
19 Reserved
20
21
22 REQ0_reg[0:2]
23
24
25
26
27
28
29
30
31
REQ0_reg[3:10]
Bits 0-15 Reserved Bit 16 Parity Error Enable 0 = disable 1 = enable System Error Enable 0 = disable 1 = enable
Bit 17
Bits 18-20 Reserved Bits 21-31 Number of PCICLK count for Master Latency Adjustment Latency Time = REQ0_reg[0:11] / PCICLK
Master 1 Latency Register (REG1) Port address : 0xf0000254 Read/Write Power-on Default : 0x000003ff
0
1
2
3 Reserved
4
5
6
7
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W90220F
8
9
10
11 Reserved
12
13
14
15
16
17 Reserved
18
19 CPURST
20 FIX
21
22 REQ1_reg[0:2]
23
24
25
26
27
28
29
30
31
REQ1_reg[3:10]
Bits 0-18 Reserved Bit 19 CPU Reset Signal 0 = disable 1 = generate CPU Reset Signal Request Priority Select 0 = Rotate Priority 1 = Fix priority
Bit 20
Bits 21-31 Number of PCICLK count for Master Latency Adjustment Latency Time = REQ1_reg[0:11] / PCICLK
Master 2 Latency Register (REG2) Port address : 0xf0000258 Read/Write Power-on Default : 0x000003ff
0
1
2
3 Reserved
4
5
6
7
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W90220F
8
9
10
11 Reserved
12
13
14
15
16
17
18 Reserved
19
20
21
22 REQ2_reg[0:2]
23
24
25
26
27
28
29
30
31
REQ2_reg[3:10]
Bits 0-20 Reserved Bits 21-31 Number of PCICLK count for Master Latency Adjustment Latency Time = REQ2_reg[0:11] / PCICLK
Master 3 Latency Register (REG3) Port address : 0xf000025c Read/Write Power-on Default : 0x000003ff
0
1
2
3 Reserved
4
5
6
7
8
9
10
11 Reserved
12
13
14
15
16
17
18 Reserved
19
20
21
22 REQ3_reg[0:2]
23
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W90220F
24
25
26
27
28
29
30
31
REQ3_reg[3:10]
Bits 0-20 Reserved Bits 21-31 Number of PCICLK count for Master Latency Adjustment Latency Time = REQ3_reg[0:11] / PCICLK
5.2.4
PARALLEL PORT INTERFACE REGISTERS
There are eleven registers included in the Parallel Port Interface (PPI) controller. The IO address map is allocated from 0xf0000370 to 0xf000037f. Table 5.2.4-1 : PPI Register Map Port Addr. BA + 0x378 BA + 0x379 BA + 0x37a BA + 0x37b BA + 0x37c BA + 0x37d BA + 0x37e BA+ 0x37f BA + 0x370 BA + 0x374 BA + 0x375 BA + 0x376 ~ BA + 0x377 Symbol DL DSR DCR FSR FCR IER IIR DR Dfifo CMD TOR Access R/W R R/W R R/W R/W R R R/W R/W R/W Description Data Line Register Device Status Register Device Control Register FIFO Status Register FIFO Control Register Interrupt Enable Register Interrupt Identification Register Data Register Data FIFO Command Register Time Out Register Reserve for PPI future extension (IO base (BA) : 0xf0000000)
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W90220F
Data Line Register (DL) Port address : 0xf0000378 Read/Write Power-on Default : --
0
1
2
3
4
5
6
7
8-bit Data Lines status Bits 0-7 Data Lines status This is the standard parallel port data register. Writing to this register will drive data to the parallel port data lines. Reads to this register return the value on the data lines.
Device Status Register (DSR) Port address : 0xf0000379 Read only Power-on Default : ---
0 BUSY# Bits 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5
1 nACK
2 PE
3 SEL
4 nFAULT
5 EMPTY
6 FULL
7 CMDtrue
Inverted version of Parallel Port Interface "BUSY" signal Version of Parallel Port Interface "nACK" signal Version of Parallel Port Interface "PError" signal Version of Parallel Port Interface "Select" signal Version of Parallel Port Interface "nFault" signal Echo device data FIFO "empty" status 0 = device data FIFO is not empty 1 = device data FIFO is empty
Bit 6
Echo device data FIFO "full" status 0 = device data FIFO is not full 1 = device data FIFO is full
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W90220F
Bit 7
"Command" pended 0 = Command Register (CMD) contains no command code 1 = A command code is in CMD not been transfered yet
This read-only register reflects the inputs on the Parallel Port Interface and some of device data FIFO and Command Register status.
Device Control Register (DCR) Port address : 0xf000037a Read/write Power-on Default : 0x0
0 Reserved Bit 2
1
2 DOE
3
4
5 nINIT
6 nAUFD#
7 nSTB#
nAck_Ien nSELIN#
Data bus output enable 0 = Data bus is drived by PPI for forward transfering 1 = Data bus is drived by peripheral device for reverse transfering This bit has no effects during "peripheral emulation mode", "standard mode", "fast standard mode" and "PS2 mode".
Bit 3
nACK interrupt enable 0 = Data bus is drived by PPI for forward transfering 1 = Data bus is drived by peripheral device for reverse transfering When this bit is set. A low-to-high transition will generate a interrupt request to CPU core.
Bit 4 Bit 5 Bit 6 Bit 7
Complement version of Parallel Port Interface "nSelectIn" signal Version of Parallel Port Interface "nInit" signal Complement version of Parallel Port Interface "nAutoFd" signal Complement version of Parallel Port Interface "nStrobe" signal
This register directly controls several output signals as well as enabling some functions. The poweron default "0x0" makes {nSelectIn, nInit, nAutoFd, nStrobe} in {high, low, high, high} state, and
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W90220F
8-bit data bus in output enable mode which are suit for "standard mode" transfering.
FIFO Status Register (FSR) Port address : 0xf000037b Read only Power-on Default : ---
0
1
2 Dfifo valid bytes
3
4
5 DA
6 SA
7 OV
Bits 0-4 Valid bytes in device data FIFO (Dfifo) During forward transfering, these bits indicate that how many bytes in 16-byte Dfifo still not be transfered yet. While during reverse transfering, these bits shows the number of data bytes which received from parallel port interface and not be read by CPU core. Bit 5 Dfifo data available 0 = Dfifo contains data bytes less than one "PWord" 1 = Dfifo contains at least one "PWord" of valid data. Bit 6 Dfifo space available 0 = Dfifo contains empty locations less than one "PWord" 1 = Dfifo contains at least one "PWord" of empty locations. Bit 7 Dfifo over/under run 0 = Dfifo is not yet over- or under-run 1 = Dfifo is already over- or under-run Once this bit is set, it will keep on set state until Dfifo or the PPI is reset.
FIFO Control Register (FCR) Port address : 0xf000037c Read/Write Power-on Default : 0x0
0 DMAen
1 FRST
2 DRST
3 PWord
4 MOD
5
6 RDTH
7
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W90220F
Bits 0
DMA mode enable A low-to-high transition of this bit will make PPI issue a DREQ to DMA controller. On receiving the corresponding DACK, PPI deasserts the DREQ. This bit will be cleared by DMA terminal-count (TC) asserting or by a CPU write cycle with data-in[0] = 0.
Bit 1
Reset Dfifo Writing a logical one to this bit will assert "Dfifo Reset" for one EXTCLK cycle. This bit will return to deasserted state automatically after "Dfifo Reset" is issued.
Bit 2
Reset Device Writing a logical one to this bit will assert "Device Reset" for one EXTCLK cycle. This bit will return to deasserted state automatically after "Device Reset" is issued.
Bit 3
PWord size 0 = PWord is 8 bits (1 byte) 1 = PWord is 32 bits (4 bytes) "PWord" defines the basic unit of Dfifo access during CPU cycle.
Bit 4-5 Device mode select IER[1] and FCR[4:5] are used to choose device operation mode. {IER[1], FCR[4:5]} 1x0 1x1 000 001 010 011 Bit 6-7 Dfifo Read Threshold These two bits define the threshold level for triggering data-available interrupt (Irpt_RDA) of Dfifo during reverse transfering.
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Device Operation Mode Test Mode Peripheral Emulation Mode Standard Mode PS2 Mode Fast Standard Mode ECP Mode
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W90220F
Read Threshold level FCR[6:7] 00 01 10 11 PWord = 1 byte 16 bytes 12 bytes 8 bytes 1 byte PWord = 4 bytes 16 bytes 12 bytes 8 bytes 4 bytes
Interrupt Enable Register (IER) Port address : 0xf000037d Read/Write Power-on Default : 0x0
0 Reserved Bits 1
1 PEMU
2 Tout_Ien
3 TC_Ien
4 Temp_Ien
5
6
7 LOOP
Rda_Ien nFault_Ien
Peripheral Emulation Mode enable 0 = Device is not operating in "Peripheral Emulation Mode" or "Test Mode" 1 = Set device to "Peripheral Emulation Mode" or "Test Mode" This bit along with FCR[4:5] are used to choose device operation mode.
Bit 2
Time-Out Interrupt (Irpt_TOUT) enable 0 = Mask Irpt_TOUT 1 = Enable Irpt_TOUT
Bit 3
DMA Terminal-Count Interrupt (Irpt_TC) enable 0 = Mask Irpt_TC 1 = Enable Irpt_TC
Bit 4
Dfifo Empty Interrupt (Irpt_TEMP) enable 0 = Mask Irpt_TEMP 1 = Enable Irpt_TEMP
Bit 5
Dfifo Read Threshold Interrupt (Irpt_RDA) enable 0 = Mask Irpt_RDA 1 = Enable Irpt_RDA
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W90220F
Bit 6
"nFault" Interrupt (Irpt_nFault) enable 0 = Mask Irpt_nFault 1 = Enable Irpt_nFault
Bit 7
Loop back enable 0 = Loop-back disable 1 = Loop-back enable During Loop-Back mode, {nStrobe, nAutoFd, nInit, nSelectIn} will be fed to {nAck, Busy, PError, nFault} internally. This mode is used only for test issue.
Interrupt Identification Register (IIR) Port address : 0xf000037e Read only Power-on Default : ---
0 Reserved
1
2 Irpt_Tout
3
4
5
6
7
Irpt_TC Irpt_Temp Irpt_RDA Irpt_nFaul Irpt_nAck t
Bits 2
Time-Out Interrupt flag "Set" situation : If IER[2] is set, and "Time out" is occured during parallel port transfering. "Reset" situation : Reset device, or CPU reads Time-Out Register (TOR) or Dfifo being accessed either by CPU or parallel port interface transfering.
Bits 3
DMA Terminal Count Interrupt flag "Set" situation : If IER[3] is set, and TC is asserted by DMA controller once DMA transfer is done. "Reset" situation : TC is deasserted by DMA controller.
Bits 4
Dfifo Empty Interrupt flag "Set" situation : If IER[4] is set, and Dfifo is empty during "forward transfering". "Reset" situation : CPU write new data into Dfifo.
Bits 5
Dfifo Read Threshold Interrupt flag "Set" situation : If IER[5] is set, and data bytes received by Dfifo are exceeded the threshold level (defined in FCR[4:5] ) during "reverse transfering".
Version 0.84
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W90220F
"Reset" situation : CPU read Dfifo such that data bytes in Dfifo are below the threshhold level. Bits 6 "nFault" Interrupt flag "Set" situation : If IER[6] is set, and a high-to-low transition is on "nFault" pin. "Reset" situation : CPU read Device Status Register (DSR). Bits 7 "nAck" Interrupt flag "Set" situation : If DCR[3] is set, and a low-to-high transition is on "nAck" pin. "Reset" situation : CPU read Device Status Register (DSR).
Data Register (DR) Port address : 0xf000037f Read only Power-on Default : ---
0
1
2
3
4
5
6
7
8-bit Data of latched Lines status Bits 0-7 Latched Line status The status of data lines of PPI will be latched into this register if a high-to-low transition is happened on "nAck" pin. This register is added to support "Peripheral Emulation Mode" operation.
Device Data FIFO (Dfifo) Port address : 0xf0000370 Read/write Power-on Default : ---
0
1
2
3
4
5
6
7
Dfifo MSB byte
8
9
10
11
12
13
14
15
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W90220F
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Dfifo LSB byte The device build-in a 16-byte data fifo to accelerate the transfer rate when using "Fast Standard Mode" or "ECP mode". The Dfifo may be 1-byte or 4-byte accessed by CPU using "PWord" basis.
Command Register (CMD) Port address : 0xf0000374 Read/write Power-on Default : ---
0
1
2
3
4
5
6
7
Pended Command Code
Bits 0-7 Pended Command Code Whenever a command code is written by CPU, a "command trasfer" will be induced immediately during "ECP forward transfering". If CMD contains a command code not been transfered yet, a "command pended" status (CMDtrue) is echoed in DSR[7]. "Reset device" or "CPU read CMD" or the pended command code is finished transfering, the CMDtrue will also be cleared.
Time Out Register (TOR) Port address : 0xf0000375 Read/write Power-on Default : ---
0 TOUTen Bits 0
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1
2
3
4 TOUTcmp
5
6
7
Time Out Counter enable
Version 0.84
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W90220F
0 = Disable Time Out counter 1 = Enable Time Out counter Bits 1-7 Time Out counter (TOUTcnt[0:6] ) comparsion value If "TOUTen" is set, the "TOUTcnt[0:6] will be reset first and then start counting whenever a new PPI transfer cycle is initiated. On detecting TOUTcnt[0:6] is equal to TOUTcmp[1:7], a "Time Out" flag will be set which in turn trigger a interrupt request (Irpt_TOUT) if IER[2] (ToutIen) is also set at that time. The tick of Time-Out Counter is about 9.175ms (OSC/(2**21) where OSC = 14.318Mhz). The maximum duration that Time-Out Counter can cover is about 1.17 sec (2**7 ticks).
5.2.5
COM PORT INTERFACE REGISTERS
W90220 Provides 2 COM ports to interface external RS232 devices. COM1 allocates 0xf00003f8 ~ oxf00003ff as its IO-space, while COM2 allocates 0xf00002f8 ~ 0xf00002ff as its IO-space. Table 5.2.5-1 : COM1 Register Map Port Addr. BA + 0x3f8, DLAB = 0 BA + 0x3f8, DLAB = 0 BA + 0x3f9, DLAB = 1 BA + 0x3f8, DLAB = 1 BA + 0x3f9, DLAB = 1 BA + 0x3fa IIR[0:7] R Interrupt Identification Register
Version 0.84
(IO base (BA) : 0xf0000000) Description Receiver Buffer Register
Symbol RBR[0:7]
Access R
THR[0:7]
W
Transmitter Holding Register
IER[3:7]
R/W
Interrupt Enable Register
DLL[0:7]
R/W
Divisor Latch Register (LS)
DLM[0:7]
R/W
Divisor Latch Register (MS)
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W90220F
BA + 0x3fa BA+ 0x3fb BA + 0x3fc BA + 0x3fd BA + 0x3fe BA + 0x3ff
FCR[0:7] LCR[0:7] MCR[0:7] LSR[0:7] MSR[0:7] TOR[0:7]
W R/W R/W R R R/W
FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register
Table 5.2.5-2 : COM2 Register Map Port Addr. BA + 0x2f8, DLAB = 0 BA + 0x2f8, DLAB = 0 BA + 0x2f9, DLAB = 1 BA + 0x2f8, DLAB = 1 BA + 0x2f9, DLAB = 1 BA + 0x2fa BA + 0x2fa BA+ 0x2fb BA + 0x2fc BA + 0x2fd BA + 0x2fe BA + 0x2ff IIR[0:7] FCR[0:7] LCR[0:7] MCR[0:7] LSR[0:7] MSR[0:7] TOR[0:7] R W R/W R/W R R R/W DLM[0:7] R/W DLL[0:7] R/W IER[3:7] R/W Interrupt Enable Register THR[0:7] W Symbol RBR[0:7] Access R Description Receiver Buffer Register
(IO base (BA) : 0xf0000000)
Transmitter Holding Register
Divisor Latch Register (LS)
Divisor Latch Register (MS)
Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register
Receiver Buffer Register (RBR) Port address : 0xf00003f8, DLAB=0 (COM1) 0xf00002f8, DLAB=0 (COM2) Read only Power-on Default : --
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W90220F
0
1
2
3
4
5
6
7
8-bit Receiver Data Bits 0-7 Receiver Data Reading this register, COM port returns 8-bit data receiving from SDI pin.
Transmitter Holding Register (THR) Port address : 0xf00002f8, DLAB=0 (COM1) 0xf00002f8, DLAB=0 (COM2) Write only Power-on Default : --
0
1
2
3
4
5
6
7
8-bit Transmit Data Bits 0-7 Transmit Data Writing to this register, COM port will sent out the data through SDO pin (THR[7] first).
Interrupt Enable Register (IER) Port address : 0xf00003f9, DLAB=0 (COM1) 0xf00002f9, DLAB=0 (COM2) Read/Write Power-on Default : 0x0
0
1
2
3
4 MOS_Ien
5
6
7
RLS_Ien THRE_Ien RDA_Ien
Bit 4
MODEM Status Interrupt (Irpt_MOS) Enable 0 = Mask Irpt_MOS 1 = Enable Irpt_MOS
Bit 5
Receiver Line Status Interrupt (Irpt_RLS) Enable 0 = Mask Irpt_RLS 1 = Enable Irpt_RLS
Bits 6
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Transmitter Holding Register Empty Interrupt (Irpt_THRE) Enable
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W90220F
0 = Mask Irpt_THRE 1 = Enable Irpt_THRE Bits 7 Receiver Data Available Interrupt (Irpt_RDA) and Time-Out Interrupt (Irpt_TOUT) Enable 0 = Mask Irpt_RDA and Irpt_TOUT 1 = Enable Irpt_RDA and Irpt_TOUT
Divisor Latch (low byte) Register (DLL) Port address : 0xf00003f8, DLAB=1 (COM1) 0xf00002f8, DLAB=1 (COM2) Read/write Power-on Default : 0x0
0
1
2
3
4
5
6
7
Baud Rate Divisor (Low Byte) Bit 0-7 Low byte of baud rate dvisor
Divisor Latch (high byte) Register (DLM) Port address : 0xf00003f9, DLAB=1 (COM1) 0xf00002f9, DLAB=1 (COM2) Read/write Power-on Default : 0x0
0
1
2
3
4
5
6
7
Baud Rate Divisor (High Byte) Bit 0-7 High byte of baud rate dvisor The 16-bit Divisor ({DLM, DLL}) is used to determine the COM port's baud rate. The equation is Baud Rate = Frequency input / {16 * [Divisor +2]}
Interrupt Identification Register (IIR) Port address : 0xf00003fa (COM1)
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Read only
Power-on Default : --Version 0.84
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W90220F
0xf00002fa (COM2)
0 FMENo Bits 0
1
2
3 DMOD
4
5 IID[0:2]
6
7 NOI
RTHo[0:1]
Status of "FIFO Mode Enable" This bit echos if "FIFO mode" is enable or not. Since "FIFO mode" is always enable, this bit always shows logical 1 when CPU reading this register.
Bit 1-2 Status of RX FIFO threshold level These bits show current setting of receiver FIFO threshold level (RTH). The meaning of RTH is defined in the following FCR description. Bit 3 DMA mode select The DMA function is not implemented in this version. Reading IIR, the bit-3 is always 0.
Bit 4-6 Interrupt Identification bits The IID[0:2] along with NOI indicate current interrupt request from COM port Bit 7 No Interrupt (NOI) pended Table 5.2.5-3 : Interrupt Control Functions IIR[4:7] ---1 0110 Priority -Highest Interrupt Type None Receiver Line Status (Irpt_RLS) Received Data Available (Irpt_RDA) Receiver FIFO Time-out (Irpt_TOUT) Interrupt Source None Overrun Error or Parity Error or Framing Error or Break Interrupt Receiver FIFO threshold level is reached Receiver FIFO is nonempty and no activities are occured in receiver FIFO during the TOR defined time duration Transmitter Holding Register Empty Interrupt Reset control -Reading the LSR
0100
Second
Receiver FIFO drops below the threshold level Reading the RBR
1100
Second
0010
Third
Transmitter Hoding Register Empty (Irpt_THRE)
Reading the IIR (if source of interrupt is Irpt_THRE) or writing into the THR
Version 0.84
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W90220F
0000
Fourth
MODEM Status (Irpt_MOS)
CTS, DSR, DCD bits chang state or RI bit changes from high to low
Reading the MSR
FIFO Control Register (FCR) Port address : 0xf00003fa (COM1) 0xf00002fa (COM2) Write only Power-on Default : 0x1
0 RTH[0:1]
1
2 Reserved
3
4 DMOD
5 TXRST
6 RXRST
7 FMEN
Bits 0-1 RX FIFO interrupt (Irpt_RDA) trigger level FCR[0:1] 00 01 10 11 Bit 4 Irpt_RDA trigger level (bytes) 01 04 08 14
DMA mode select The DMA function is not implemented in this version. Reset TX FIFO Seting this bit will generate 1 OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX-pointer is cleared to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. Reset RX FIFO Seting this bit will generate 1 OSC cycle reset pulse to reset RX FIFO. The RX FIFO becomes empty (RX-pointer is cleared to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. FIFO mode enable The UART0 and UART1 are always operated on FIFO mode. Writing this bit has no effect while reading this bit always get logical one.
Bit 5
Bit 6
Bit 7
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W90220F
Line Control Register (LCR) Port address : 0xf00003fb (COM1) 0xf00002fb (COM2) Read/Write Power-on Default : 0x0
0 DLAB Bits 0
1 BREAK
2 SPAR
3 EPAR
4 PAR
5 STOP
6 WLEN
7
Divisor Latch Access Bit 0 = "2F8/3F8" and "2F9/3F9" are used to access RBR, THR or IER. 1 = "2F8/3F8" and "2F9/3F9" are used to access Divisor Latch Registers (DLL, DLM).
Bit 1
Break Control Bit When this bit is set to a logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0). This bit affects SOUT only and has no effect on the transmitter logic. Stick Parity Enable 0 = Disable Stick Parity 1 = The parity bit is transmitted and checked as a logic 1 if bit-3=0 (odd parity), or as a logic 0 if bit-3=1 (even parity). This bit has effects only when bit-4 (Parity Bit Enable) is set.
Bit 2
Bit 3
Even Parity Enable 0 = Odd number of logic 1s is transmitted or checked in the data word bits and parity bit. 1 = Even number of logic 1s is transmitted or checked in the data word bits and parity bit. This bit has effects only when bit-4 (Parity Bit Enable) is set.
Bit 4
Parity Bit Enable 0 = Praity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated of checked between the "last data word bit" and "stop bit" of the serial data.
Bit 5
Number of "Stop bit" 0 = One "stop bit" is generated in the transmitted data. 1 = One and a half "stop bit" is generated in the transmitted data when 5-bit word length is selected. Two "stop bit" is generated when 6-, 7- and 8-bit word length is selected.
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W90220F
Bits 6-7 Word Length Select LCR[6:7] 00 01 10 11 Character length 5 bits 6 bits 7 bits 8 bits
Modem Control Register (MCR) Port address : 0xf00003fc (COM1) 0xf00002fc (COM2) Read/Write Power-on Default : 0x0
0
1 Reserved
2
3 LOOP
4 OUT2#
5 OUT1#
6 RTS#
7 DTR#
Bits 3
Enable Loop-Back mode 0 = Disable 1 = When loop-back is enable, the following signals is connected internally. SOUT connects to SIN RTS# internally and SOUT pin is fixed logic 1. pin is fixed logic 1. DTR# connects to DSR# internally and DTR# pin is fixed logic 1. connects to CTS# internally and RTS# OUT1# connects to RI# internally and OUT1# pin is fixed logic 1.
OUT2# connects to DCD# internally and OUT2# pin is fixed logic 1. Bit 4 Bit 5 Bit 6 Bit 7 Complement version of OUT2# (user-designated output) signal Complement version of OUT1# (user-designated output) signal Complement version of RTS# (Request-To-Send) signal Complement version of DTR# (Data-Terminal-Ready) signal
Writing 0x00 to MCR set DTR#, RTS#, OUT1# and OUT2# to logic 1s, while writing 0x0f to MCR reset DTR#, RTS#, OUT1# and OUT2# to logic 0s.
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W90220F
Line Status Register (LSR) Port address : 0xf00003fd (COM1) 0xf00002fd (COM2) Read only Power-on Default : ---
0 Err_RCVR Bits 0
1 TEMT
2 THRE
3 BI
4 FE
5 PE
6 OE
7 DR
RX FIFO Error 0 = RX FIFO works normally 1 = There is at least one parity error (PE), framing error (FE) or break indication (BI) in the FIFO. LSR[0] is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO.
Bit 1
Transmitter Empty 0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift Register (TSR) are not empty. 1 = Both THR and TSR are empty.
Bit 2
Transmitter Holding Register Empty 0 = THR is not empty. 1 = THR is empty. The THRE bit is set when the last data word of TX FIFO is transferred to TSR. This bit is reset concurrently with the loading of the THR (or TX FIFO) by the CPU. This bit also causes the UART to issue an interrupt (Irpt_THRE) to the CPU when IER[6]=1.
Bit 3
Break Interrupt indicator This bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
Bit 4
Framing Error indicator This bit is set to a logic 1 whenever the received character did not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Bit 5
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Parity Error indicator
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W90220F
This bit is set to a logic 1 whenever the received character did not have a valid "parity bit". Bit 6 Overrun Error indicator An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register. The ccharacter in the shift register is overwritten, but it is not transferred to the RX FIFO. OE is indicated to the CPU as soon as it happens and is reset whenever the CPU reads the contents of the LSR. Bit 7 RX FIFO Data Ready 0 = RX FIFO is empty 1 = RX FIFO contains at least 1 received data word. LSR[3:5] (BI, FE, PE) is revealed to the CPU when its associated character is at the top of the RX FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR. LSR[3:6] (BI, FE, PE, OE) are the error conditions that produce a "receiver line status interrupt" (Irpt_RLS) when IER[5]=1. Read LSR clear Irpt_RLS. Writing LSR is a null operation (not suggested).
Modem Status Register (MSR) Port address : 0xf00003fe (COM1) 0xf00002fe (COM2) Read only Power-on Default : ---
0 DCD# Bits 0 Bits 1 Bits 2 Bits 3 Bits 4
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1 RI#
2 DSR#
3 CTS#
4 DDCD
5 TERI
6 DDSR
7 DCTS
Complement version of Data Carrier Detect (DCD#) input Complement version of Ring Indicator (RI#) input Complement version of Data Set Ready (DSR#) input Complement version of Clear to Send (CTS#) input DCD# state change
Version 0.84
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W90220F
This bit is set whenever DCD# input has changed state, and it will be reset if the CPU reads the MSR. Bits 5 Tailing edge of RI This bit is set whenever TI# input has changed from high to low, and it will be reset if the CPU reads the MSR. Bits 6 DSR# state change This bit is set whenever DSR# input has changed state, and it will be reset if the CPU reads the MSR. Bits 7 CTS# state change This bit is set whenever CTS# input has changed state, and it will be reset if the CPU reads the MSR. Whenever either of MSR[4:7] is set to logic 1, a Modem Status Interrupt is generated if IER[4]=1. Writing LSR is a null operation (not suggested).
Time Out Register (TOR) Port address : 0xf00003ff (COM1) 0xf00002ff (COM2) Read/Write Power-on Default : 0x0
0 TOUT_en Bits 0
1
2
3
4 TOUT_cmp
5
6
7
Time-Out (interrupt) enable The feature of Receiver Time-Out (interrupt) is enable only when TOR[0] = IER[7] = 1.
Bits 1-7 Time-Out (interrupt) comparator The Time-Out counter is reset and start counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of Time-Out counter (TOUT_cnt) is equal to that of Time-Out comparator (TOUT_cmp), a Receiver Time-Out interrupt Irpt_ TOUT) is generated if TOR[0] = IER[7] = 1.
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W90220F
A new incoming data word or RX FIFO empty clears Irpt_TOUT.
5.2.6
SYNCHRONOUS SERIAL INTERFACE REGISTERS
There are five registers included in the Synchronous Serial Interface (SSI) controller. The IO address map is allocated from 0xf0000380 to 0xf000038a. Table 5.2.6-1 : SSI Register Map Port Addr. BA + 0x380 BA + 0x384 BA + 0x386 BA + 0x388 BA + 0x38a Symbol Dfifo CFGH CFGL CTRL STUS Access R/W R/W R/W R/W R/W Description Data FIFO High Configuration Register Low Configuration Register Control Register Status Register (IO base (BA) : 0xf0000000)
Data FIFO Register (Dfifo) Port address : 0xf0000380 Read/Write Power-on Default : --
0
1
2
3
4
5
6
7
Dfifo MSB Byte
8
9
10
11
12
13
14
15
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W90220F
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Dfifo LSB byte
The device build-in a 48x16 or 24x32 data fifo to accelerate the transfer rate. The Dfifo may be 16-bit or 32-bit accessed by CPU, the type of reading, 16-bit or 32-bit depends on RX_FIFO type, and the type of writing, 16-bit or 32-bit depends on TX_FIFO type. Bits 0-31 PCM data in/out, Whether the MSB bits are sign- or zero-extension depends on MEXT (CFGH[6]).
High Configuration Register (CFGH) Port address : 0xf0000384 Read/Write Power-on Default : 0x0000
0 SSIEN
1 LOOP
2 MASTER
3 LFMOD
4 Reserved
5 FACT
6 MEXT
7 SLEN[0]
8
9
10
11
12
13
14
15
SLEN[1:4] Bits 0 SSI Enable 0 = SSI disable 1 = SSI enable Loop back enable 0 = disable 1 = enable
WPF[0:3]
Bit 1
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W90220F
Bit 2
Master mode enable 0 = Slave mode enable. SYNC, SCLK are inputs. 1 = Master mode enable. SYNC, SCLK are outputs. Long Framing Mode 0 = Short framing The first data will be available on the next SCLK cycle as SYNC is active. In this mode, SYNC width is 1 SCLK. 1 = Long framing The first data will be available on the same SCLK cycle as SYNC is active. In this mode, SYNC width is 1 SLEN. Reserved Frame active level 0 = active high 1 = active low RX-FIFO MSB extension 0 = fill 0 in redundant MSBs of RX-FIFO 1 = non-implement
Bit 3
Bit 4 Bit 5
Bit 6
Bit 7-11 Serial word length Word length = SLEN[0:4] + 1. The word length supported by SSI is from 1 to 32 bits. SLEN[0:4] configure TX/RX also. if SLEN[0:4] <= 15, FIFO will be configured as 48x16. if 15 < SLEN[0:4] <= 31, FIFO will be configured as 24x32. Bit 12-15 Words per Frame Words per frame = WPF[0:3] + 1. (max. 16 words/frame)
Low Configuration Register (CFGL) Port address : 0xf0000386 Read/write Power-on Default : 0x0000
0
1
2
3 BPF[0:7]
4
5
6
7
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W90220F
8
9
10
11
12
13
14
15
SCLKDIV[0:7]
Bit 0-7
Number of bits per frame Bits per frame = BPF[0:7] + 1. (max. 256 bits/frame)
Bit 8-15
Serial clock divider On master mode,the SCLK is an output and its frequency is SCLK frequency = EXTCLK / (2*(SCLKDIV+1))
Control Register (CTRL) Port address : 0xf0000388 Read/Write Power-on Default : 0x0000
0 DVRST
1 TXRST
2 RXRST
3
4
5
6
7 IntRxen
RXTH[0:1]
TXTH[0:1]
8 IntTXen
9 IntERRen
10
11
12 Reserved
13
14
15
Bits 0
Device reset This is a self-clear bit, ie. set this bit to 1, it will be clear to 0 automatically after 1 EXTCLK. When this bit is set, all registers will be set to its default value and the controller will be also set to its initial states. Reset TX-FIFO This is a self-clear bit, ie. set this bit to 1, it will be clear to 0 automatically after 1 EXTCLK. When this bit is set, The TX-FIFO pointer will be cleared to 0, the TX-FIFO is empty immediately. Reset RX-FIFO This is a self-clear bit, ie. set this bit to 1, it will be clear to 0 automatically after 1 EXTCLK. When this bit is set, The RX-FIFO pointer will be cleared to 0, the RX-FIFO is empty immediately.
Version 0.84
Bit 1
Bit 2
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W90220F
Bit 3-4 RX-FIFO threshold level 00 = RX-FIFO full 01 = 3/4 RX-FIFO 10 = 1/2 RX-FIFO 11 = RX-FIFO non-empty Bit 5-6 TX-FIFO threshold level 00 = TX-FIFO empty 01 = 1/4 TX-FIFO 10 = 1/2 TX-FIFO 11 = TX-FIFO non-full Bit 7 RX-FIFO interrupt enable 0 = disable 1 = enable TX-FIFO interrupt enable 0 = disable 1 = enable RX-FIFO overrun interrupt enable 0 = disable 1 = enable
Bit 8
Bit 9
Bit 10-15 Reserved
Status Register (STUS) Port address : 0xf000038a Read/Write Power-on Default : --
0 RXDA
1 TXSA
2 RXERR
3
4 Reserved
5
6
7 IntRX
8 IntTX Bits 0
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9 INTRERR
10
11
12 Reserved
13
14
15
RX-FIFO data available
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W90220F
0 = There is no valid data word in RX-FIFO. 1 = There is at least one valid data word in RX-FIFO. Bit 1 TX-FIFO space available 0 = There is no space available in TX-FIFO. 1 = The TX-FIFO can still accept at least one data word. RX-FIFO overrun 0 = The RX-FIFO works well. 1 = The RX-FIFO is already overrun. Once the RX-FIFO is overrun, this bit will keep active until RX-FIFO is reset.
Bit 2
Bit 3-6 Reserved Bit 7 RX-FIFO interrupt request 0 = No RX-FIFO interrupt request 1 = A RX-FIFO interrupt request is pending Set = Valid data words in RX-FIFO exceeds the threshold level. Reset = Valid data words in RX-FIFO drops below the threshold level. TX-FIFO interrupt request 0 = No TX-FIFO interrupt request 1 = A TX-FIFO interrupt request is pending Set = Valid data words in TX-FIFO drops below the threshold level. Reset = Valid data words in TX-FIFO exceeds the threshold level RX-FIFO overrun interrupt request 0 = No RX-FIFO overrun interrupt request 1 = A RX-FIFO overrun interrupt request is pending Set = When RX-FIFO is overrun. Reset = Reset RX-FIFO or reset device.
Bit 8
Bit 9
Bit 10-15 Reserved
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W90220F
5.2.7 TIMER REGISTERS
There are four registers included in the Timer. The IO address map is allocated from 0xf0000040 to 0xf0000043. Table 5.2.7-1 Timer Register Map Port Addr. BA + 0x40 BA + 0x41 BA + 0x42 BA + 0x43 Symbol TCR1 TICR1 TCR2 TICR2 Access R/W R/W R/W R/W Description Timer Control Register 1 Timer Initial Control Register 1 Timer Control Register 2 Timer Initial Control Register 2 (IO base (BA) : 0xf0000000)
Timer Control Register1 (TCR1) Port address : 0x00000040 Read/Write Power-on Default : --
0 TI
1 CE
2 IE
3 23 Reserved
24 Pre-scale
31
Bit 0
Timer interrupt bit : The timer sets this bit to one to indicate that it has decremented to zero. this bit remain one until software sets it to zero. Counter Enable bit : Setting the CE bit to one causes the timer to begin decrementing Setting the CE bit to zero stops the timer. Interrupt Enable bit : When IE is set to one and the counter decrements to zero, the timer asserts its interrupt signal to interrupt CPU.
Bit1
Bit2
Bit24_31 Pre-Scalar : A pre-scalar value can be used to divide the input clock.
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Timer Initial Control Register1 (TICR1) Port address : 0xf0000041 Read/Write Power-on Default : --
0 7 reserved
8 31 Timer Initial Count
Bit8_31 : A 24-bit register for the initial counter value.
Timer Control Register2 (TCR2) Port address : 0xf0000042 Read/Write Power-on Default : --
0 TI
1 CE
2 IE
3 23 Reserved
24 Pre-scale
31
Bit 0
Timer interrupt bit : The timer sets this bit to one to indicate that it has decremented to zero. this bit remain one until software sets it to zero. Counter Enable bit : Setting the CE bit to one causes the timer to begin decrementing Setting the CE bit to zero stops the timer. Interrupt Enable bit : When IE is set to one and the counter decrements to zero, the timer asserts its interrupt signal to interrupt CPU.
Bit1
Bit2
Bit24_31 Pre-Scalar : A pre-scalar value can be used to divide the input clock.
Timer Initial Control Register1 (TICR2) Port address : 0xf0000043 Read/Write Power-on Default : --
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W90220F
0 7 reserved
8 31 Timer Initial Count
Bit8_31 : A 24-bit register for the initial counter value. Two 24-bit decrementing timers will be implemented, corresponding to the TCR1, TICR1 and TCR2, TICR2 independently. When the timers interrupt enable bit is set to one and the counter decrements to zero, the timer will assert the associated interrupt signal. The interrupt signal will assert one of the 32 external interrupts defined by the EI bits in the control register. When a timer reaches zero, the timer hardware reloads the counter with the value from the timer initial count register and continues decrementing.
75
Winbond.
Version 0.84
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
W90220F
6 6.1
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Ambient temperature ....................................................................................................... 0 C ~ 70 C Storage temperature ......................................................................................................... -40 C ~ 125C Voltage on any pin ........................................................................................................... Vss-0.5V ~ Vcc+0.5V Power supply voltage ....................................................................................................... 7V Injection current (latch-up testing) ................................................................................... 100mA Operating power dissipation ............................................................................................. 30mA/Mhz
6.2
DC Specifications
(Normal test conditions : VDD5V = 5.0V+/- 5%, VDDi/VDDp/VDDl = 3.3V+/- 5%, TA = 0 C ~ 70 C unless otherwise specified) SYMBOL VDD5V VDDi/VDDp VIL VIH VOL VOH ICC IIH IIL IIHP IILP PARAMETER Power Supply Power Supply Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supply Current Input High Current Input Low Current IOUT = 2,4,8 mA IOUT = -1,2,4 mA Fcpu = 100Mhz VIN = 2.4 V VIN = 0.4 V
(*1) (*2)
CONDITION
MIN 4.75 3.14
MAX 5.25 3.46 0.8
UNIT V V V V
2.0 VSS+ 0.4 2.4 300 10 -10 -45 -10 10 -15
V V mA A A A A
(*2)
(*1)
Input High Current (pull-up) VIN = 2.4 V Input Low Current (pull-up) VIN = 0.4 V
(*3)
(*3)
Note *1 : Inpt leakage current (IIL, IIH) include those bi-directional pins which are in "input" mode (output disable). *2 : Pins of 4mA sink capability include : ROMMEN#, DACK[0:1], CS[0:1], TC[0:1], DTR1#, RTS1#,
76
Winbond.
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The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
W90220F
SOUT1, SOUT2. RAS#[0:3], RCS#[0:3], ROM_OE#, ROM_RW#, IOR, IOW, nAutoFd, nStrob, SelectIn, nInit, SDO, MD[0:31], DD[0:7], PCICLK, SCLK, SYNC. Pins of 8mA sink capability include : CAS#[0:3], MA[0:11], WE#, PCIRST, GNT#[0:1], ED[0:7], C/BE[0:3], PDA[0:31], STOP#, PERR#, TRDY#, DEVSEL#, FRAME#, IRDY#, PPAR. *3 : Inputs with internal pull-up resistor include : PREQ#[0:1], SERR#, INTA#, INTB#, INTC#, INTD#, CTS1#, DSR1#, RI1#, DCD1#. Pins of 6mA sink capability include :
6.3
AC Specifications
6.3.1 Memory controller
Fig 6.3.1-1 : DRAM AC Timimg PCLK
tav
MA11 - MA0
tds tdh
MD31 - MD0
trv1 trv2 tcv1 tcv2
RAS3# - RAS0# CAS3# - CAS0#
twv
WE#
Symbol Parameter RAS# valid delay ref. to PCLK rising trv1 trv2 tcv1 tcv2 twv tds tdh tav RAS# valid delay ref. to PCLK rising CAS# valid delay ref. to PCLK rising RAS# valid delay ref. to PCLK rising WE# valid delay ref. to PCLK rising Memory data setup time Memory data hold time Memory address valid delay
Min
Max
Unit ns ns ns ns ns ns ns ns
Fig 6..3.1-2 Flash ROM Write Timimg
77
Winbond.
Version 0.84
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
W90220F
PCLK MA11 - MA0
tas
RCS0# RCS3# ROMRW# ROMOE#
tds tcs twp
MD31 - MD0
tdh
Symbol Parameter Address setup time tas tcs tds tdh twp Chip select setup time Data setup time Data hold time Flash ROM write pulse width
Min
Max
Unit ns ns ns ns
7
PCLK
Fig 6.3.1-3 ROM Read Timimg PCLK
tac
MA11 - MA0
tcs
RCS0# RCS3# ROMRW#
top
ROMOE#
tds
MD31 - MD0
tdh
Symbol Access time tac tcs
78
Winbond.
Parameter
Min 3
Max
Unit PCLK ns
Version 0.84
Chip select setup tome
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
W90220F
top tds tdh
Output enable pulse Data setup tome Data hold time
ns ns ns
7
PACKAGE DIMENSIONS
The W90220 is packaged in a 208-pin PQFP package. The following figure shows its mechanical dimension
HD D
208 157
Symbol
Dimension in inch
Dimension in mm
Min
0.004 0.122 0.006 0.004 1.097 1.097 0.016 1.193 1.193 0.012 0.043
Nom
Max
0.145
Min
0.10
Nom
Max
3.68
1
156
E HE
52
105
A A1 A2 b c D E e HD HE L L1 y 0
Note:
c
0.127 0.008 0.006 1.102 1.102 0.020 1.205 1.205 0.020 0.051
0.132 0.010 0.010 1.107 1.107 0.024 1.217 1.217 0.028 0.059 0.004
3.10 0.15 0.10 27.87 27.87 0.40 30.30 30.30 0.30 1.10
3.23 0.20 0.15 28.00 28.00 0.50 30.60 30.60 0.50 1.30
3.35 0.25 0.25 28.13 28.13 0.60 30.90 30.90 0.70 1.50 0.10
0
10
0
10
53
e
b
104
A
A2 See Detail F Seating Plane A1 y L1 Detail F L
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
79
Winbond.
Version 0.84
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from

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